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3 Commits

Author SHA1 Message Date
Patrick Delaunay
e74b74c528 dts: stm32mp1: clock tree update 
- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2019-02-09 07:50:57 -05:00
Patrick Delaunay
a674313c2c dts: import stm32mp1 device tree from linux kernel 
This patch rebase the stm32mp1 device tree source from
linux kernel v4.18-rc1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2018-07-20 15:55:05 -04:00
Patrick Delaunay
3d2d115a30 dts: add device tree for STM32MP157C-ED1 board 
Add minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCard

Waiting Kernel upstream for alignment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2018-03-19 16:14:22 -04:00