4 Commits

Author	SHA1	Message	Date
Simon Glass	401d1c4f5d	common: Drop asm/global_data.h from common header ... Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>	2021-02-02 15:33:42 -05:00
Bin Meng	52dc7ae749	riscv: fu540: Use correct API to get L2 cache controller base address ... At present fdtdec_get_addr() is used to get L2 cache controller base address. This only works for a fixed #address-cells and #size-cells. Change to use fdtdec_get_addr_size_auto_parent() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>	2020-08-25 09:33:16 +08:00
Heinrich Schuchardt	6a43e3a167	riscv: sifive: fu540: redundant initialization ... We should not initialize a variable if the value is overwritten before being read. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>	2020-08-14 14:39:14 +08:00
Pragnesh Patel	5ce50206ed	riscv: sifive: fu540: enable all cache ways from U-Boot proper ... Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2020-07-03 15:09:06 +08:00