3 Commits

Author	SHA1	Message	Date
Bin Meng	4b3f5ed5ac	riscv: Move trap handler codes to mtrap.S ... Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>	2018-12-18 09:56:27 +08:00
Bin Meng	b5369c5813	riscv: Make start.S available for all targets ... Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>	2018-10-03 17:48:14 +08:00
Bin Meng	2fab2e9c88	riscv: Add a helper routine to print CPU information ... This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>	2018-10-03 17:47:55 +08:00