Simon Glass
8c103c33fb
dm: dts: Convert driver model tags to use new schema
...
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.
Signed-off-by: Simon Glass <sjg@chromium.org >
2023-02-14 09:43:26 -07:00
Chin-Ting Kuo
d37b4f37ea
arm: dts: aspeed: Update SPI flash node settings
...
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
AST2500:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x37ffffff
- SPI2:
CS number: 2
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x38000000 - 0x3fffffff
AST2600:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x3fffffff
- SPI2:
CS number: 3
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x50000000 - 0x5fffffff
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com >
2022-09-13 12:08:40 -04:00
Joel Stanley
dedf8e3186
ARM: dts: ast2600: Update SDHCI nodes
...
Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.
Signed-off-by: Joel Stanley <joel@jms.id.au >
2022-07-06 14:31:29 -04:00
Joel Stanley
b45768ebfe
ARM: dts: ast2600-evb: Add I2C devices
...
The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7,
and a LM75 temp sensor on bus 8.
Signed-off-by: Joel Stanley <joel@jms.id.au >
2022-07-06 14:30:51 -04:00
Joel Stanley
3ad1d85d3c
ARM: dts: ast2600-evb: Remove redundant pinctrl
...
Now that these are in the dtsi we don't need them in the EVB device
tree.
Signed-off-by: Joel Stanley <joel@jms.id.au >
2022-07-06 14:30:51 -04:00
Billy Tsai
5b66ebb4e9
ARM: dts: ast2600: Add PWM to device tree
...
Add the PWM node and enable it for AST2600 EVB
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com >
Reviewed-by: Simon Glass <sjg@chromium.org >
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com >
2022-03-25 13:35:50 -04:00
Dylan Hung
abc75897ca
ARM: dts: ast2600: Add MDIO devices
...
There are 4 MDIO bus controllers in AST2600 SOC. Each of them can
connect to one or more PHY chips and is flexible to work with the 4 MAC
devices in AST2600. On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY
chips used by MAC 0,1,2,3 respectively.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com >
Reviewed-by: Ramon Fried <rfried.dev@gmail.com >
2022-01-18 12:48:17 -05:00
Chia-Wei Wang
f05522749c
ARM: dts: ast2600: Add ACRY to device tree
...
Add ACRY DTS node and enable it for AST2600 EVB.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com >
Reviewed-by: Joel Stanley <joel@jms.id.au >
2021-11-17 17:05:00 -05:00
Joel Stanley
a2f16d0073
ARM: dts: ast2600: Add HACE to device tree
...
Add HACE DTS node and enable it for AST2600 EVB.
Signed-off-by: Joel Stanley <joel@jms.id.au >
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com >
2021-11-17 17:05:00 -05:00
Chia-Wei, Wang
ec55a1df39
ARM: dts: aspeed: Add AST2600 SoC support
...
AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.
AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com >
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com >
2021-01-18 15:23:06 -05:00
