Thomas Chou 
							
						 
					 
					
						
						
							
						
						e3e872604d 
					 
					
						
						
							
							net: altera_tse: add mSG-DMA support  
						
						... 
						
						
						
						The Modular Scatter-Gather DMA core is a new DMA core to work
with the Altera Triple-Speed Ethernet MegaCore. It replaces the
legacy Scatter-Gather Direct Memory Access (SG-DMA) controller
core. Please find details on the "Embedded Peripherals IP User
Guide" of Altera.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de > 
						
						
					 
					
						2015-11-12 08:26:59 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						38fa4aca8a 
					 
					
						
						
							
							net: altera_tse: add priv ops to prepare msgdma support  
						
						... 
						
						
						
						Add priv ops to prepare msgdma support. These ops are dma type
specific.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de > 
						
						
					 
					
						2015-11-12 08:26:59 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						4c8df1d359 
					 
					
						
						
							
							net: altera_tse: use BIT macro  
						
						... 
						
						
						
						Replace numerical bit shift with BIT macro
in altera_tse
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de >
Reviewed-by: Chin Liang See <clsee@altera.com >
Reviewed-by: Jagan Teki <jteki@openedev.com >
Acked-by: Joe Hershberger <joe.hershberger@ni.com > 
						
						
					 
					
						2015-11-06 12:56:47 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						14fb536990 
					 
					
						
						
							
							net: altera_tse: remove the useless parenthesis  
						
						... 
						
						
						
						Remove the useless parenthesis.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de >
Reviewed-by: Chin Liang See <clsee@altera.com >
Acked-by: Joe Hershberger <joe.hershberger@ni.com > 
						
						
					 
					
						2015-11-06 12:56:47 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						13146ec938 
					 
					
						
						
							
							net: altera_tse: fix packed and aligned attribute  
						
						... 
						
						
						
						Fix packed and aligned attribute warnings.
WARNING: __packed is preferred over __attribute__((packed))
#14 : FILE: drivers/net/altera_tse.h:14:
+#define __packed_1_    __attribute__ ((packed, aligned(1)))
WARNING: __aligned(size) is preferred over
__attribute__((aligned(size)))
#14 : FILE: drivers/net/altera_tse.h:14:
+#define __packed_1_    __attribute__ ((packed, aligned(1)))
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de >
Reviewed-by: Chin Liang See <clsee@altera.com >
Acked-by: Joe Hershberger <joe.hershberger@ni.com > 
						
						
					 
					
						2015-11-06 12:56:46 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						2cd0a52ece 
					 
					
						
						
							
							net: altera_tse: use data type u32 for regs and desc  
						
						... 
						
						
						
						Use data type u32/u16/u8 for regs and desc, as it is more
portable.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de >
Reviewed-by: Chin Liang See <clsee@altera.com >
Acked-by: Joe Hershberger <joe.hershberger@ni.com > 
						
						
					 
					
						2015-11-06 12:56:46 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						fba54a5d61 
					 
					
						
						
							
							net: altera_tse: remove unused macro and regs def  
						
						... 
						
						
						
						Remove unused macro and regs def.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de >
Reviewed-by: Chin Liang See <clsee@altera.com >
Acked-by: Joe Hershberger <joe.hershberger@ni.com > 
						
						
					 
					
						2015-11-06 12:56:46 +08:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						96fa1e4385 
					 
					
						
						
							
							net: convert altera_tse to driver model and phylib  
						
						... 
						
						
						
						Convert altera_tse to driver model and phylib.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Reviewed-by: Marek Vasut <marex@denx.de >
Reviewed-by: Simon Glass <sjg@chromium.org > 
						
						
					 
					
						2015-10-23 14:55:48 +08:00 
						 
				 
			
				
					
						
							
							
								Mike Frysinger 
							
						 
					 
					
						
						
							
						
						8ef583a035 
					 
					
						
						
							
							miiphy: convert to linux/mii.h  
						
						... 
						
						
						
						The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org > 
						
						
					 
					
						2011-01-09 18:06:50 +01:00 
						 
				 
			
				
					
						
							
							
								Thomas Chou 
							
						 
					 
					
						
						
							
						
						c960b13ed2 
					 
					
						
						
							
							net: add altera triple speeds ethernet mac driver  
						
						... 
						
						
						
						This driver supports the Altera triple speeds 10/100/1000 ethernet
mac.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw >
Signed-off-by: Ben Warren <biggerbadderben@gmail.com > 
						
						
					 
					
						2010-05-03 14:52:49 -07:00