Rockchip RK3399 and RK3588 SoCs can support wide range of bootflows.
Without full bootflow commands, it can be difficult to
figure out issues if any, hence enable by default.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shantur Rathore <i@shantur.com>
OPTEE gets loaded into a memory region overlapping with the ram disk.
Fix the ramdisk address so it doesn't overlap with the OPTEE memory
region.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rv1126 requires OPTEE as it provides pcsi support. Mainline Linux
kernel will fail to boot without this.
Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided
when building.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the DM_ETH_PHY and PHY_REALTEK now that the designware ethernet
driver call eth_phy_set_mdio_bus() to assist with resetting the eth PHY
during probe.
Fixes ethernet on the v1.21 hw revision of Radxa ROCK Pi E:
=> mdio list
ethernet@ff540000:
1 - RealTek RTL8211F <--> ethernet@ff540000
=> net list
eth0 : ethernet@ff540000 86:e0:c0:ea:fa:a9 active
eth1 : ethernet@ff550000 86:e0:c0:ea:fa:a8
=> dhcp
Speed: 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.1.114 (1004 ms)
Reported-by: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some ethernet PHY require being reset before a phy-id can be read back
on the MDIO bus. This can result in the following message being show
on e.g. a Radxa ROCK Pi E v1.21 with a RTL8211F ethernet PHY.
Could not get PHY for ethernet@ff540000: addr -1
Add support to designware ethernet driver to reset eth phy by calling
the eth phy uclass function eth_phy_set_mdio_bus(). The call use NULL
as bus parameter to not set a shared mdio bus reference that would be
freed when probe fails. Also add a eth_phy_get_addr() call to try and
get the phy addr from DT when DM_MDIO is disabled.
This help fix ethernet on Radxa ROCK Pi E v1.21:
=> mdio list
ethernet@ff540000:
1 - RealTek RTL8211F <--> ethernet@ff540000
Reported-by: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The CONFIG_SPL_STACK for rk3036 is removed in below patch, need to add
it back.
Fixes: f113d7d303 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This patch add support for additional bank info used by LPDDR5.
Series-version: 2
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Pull request smbios-2024-04-rc2
* In smbios command
- write 'Not Specified' for missing strings
- show correct table size for SMBIOS2.1 entry point
- adjust formatting of handle numbers
- add missing colon after UUID
* In generated SMBIOS table
- avoid introducing 'Unknown' string for missing properties
- provide RISC-V vendor ID in the type 4 structure
- provide the correct chassis handle in structure type 2
* Rename Structure Table Maximum Size field in SMBIOS 3 entry point
In the SMBIOS 3 entry point the Structure Table Maximum Size field was
incorrectly named max_struct_size. A Maximum Structure Size field only
exists in the SMBIOS 2.1 entry point and has a different meaning.
Call the Structure Table Length field table_maximum_size.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Only the SMBIOS 2.1 entry point has a field for the maximum structure size.
As we have switched to an SMBIOS 3 entry point remove the superfluous
calculation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The SMBIOS table size for SMBIOS2.1 entry points is in field 'Structure
Table Length' (offset 0x16) and not in field 'Maximum Structure Size'
(offset 0x08).
Rename the receiving variable max_struct_size to table_maximum_size
to avoid future confusion.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
For RISC-V CPUs the SMBIOS Processor ID field contains
the Machine Vendor ID from CSR mvendorid.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The SMBIOS specification describes: "If a string field references no string,
a null (0) is placed in that string field."
Accordingly we should avoid writing a string "Unknown" to the SMBIOS table.
dmidecode displays 'Not Specified' if the string number is 0.
Commit 00a871d34e ("smbios: empty strings in smbios_add_string()")
correctly identified that strings may not have length 0 as two
consecutive NULs indentify the end of the string list. But the suggested
solution did not match the intent of the SMBIOS specification.
Fixes: 00a871d34e ("smbios: empty strings in smbios_add_string()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
When no string is present in a table, next_ptr points to the same
location as eos. When calculating the string table length, we would only
reserve one \0. By spec a SMBIOS table has to end with two \0\0 when no
strings a present.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
A missing string value is indicated by a string index of 0. In this case
print 'Not Specified' like the Linux dmidecode command does.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* Add RISC-V falcon mode documentation
* Add Clang build support
* Add cmd to detect Debug Trigger Extension support
* Add PWM setting for Unmatched board
* Add Milk-V Duo board support
* Add new device node and enable new config option for VisionFive2 board
* Add second virtio device for RISC-V QEMU
Add the axp15060 regulator device. OpenSBI uses this device to perform
board reset and shutdown.
Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
JH7110 has a power management unit controller node. Add this node.
This device is used by OpenSBI during board reset/shutdown.
Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Configure the pad drive strength register for both PHYs.
The values correspond to what can be found in the Linux DTS
for VisionFive2 v1.3b.
Pad drive strength configuration is required for the phy0 to work correctly
with 100Mbit links.
Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This ports the pad drive strength register configuration which can be
already found in the Linux driver for this PHY.
Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The VisionFive 2 board supports saving the u-boot environment settings
are saved to on-board SPI flash. However the defconfig enables both
ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH, preventing the "saveenv" command
to work. Fix that by disabling ENV_IS_NOWHERE.
Fixes: 7d79bed00c ("configs: starfive: Enable environment in SPI flash support")
Reported-by: E Shattow <lucent@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The -ffixed-gp option of GCC has an exact equivalent of -ffixed-x3 in
Clang.
Signed-off-by: kleines Filmröllchen <filmroellchen@serenityos.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
QEMU RISC-V supports multiple virtio devices, but only tries to boot to
the first one. Enable support for a second virtio device, that is useful
for instance to boot on a disk image + an installer. Ideally that should
be made dynamic, but that's a first step.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
handled dynamically by looking at the PCB version in the EEPROM in order
to have a single u-boot version for both versions of the board. While
the "model" property is correctly handled, the "compatible" one is
always the the one of version 1.3b.
This patch add support for dynamically configuring that property.
Fixes: 9b7060bd15 ("riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add documentation to introduce the Falcon Mode on RISC-V.
In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel.
Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Latest RPi5 EEPROM firmware versions after "DATE: 2023/10/30", has changed
kernel load address from 0x80000 to 0x200000 which break boot process.
Switch to position independent code to be able to boot the same binary
on top of different EEPROM firmware versions.
Tested on:
Raspberry Pi 5 Model B Rev 1.0
Raspberry Pi 4 Model B Rev 1.1
Raspberry Pi 3 Model B Plus Rev 1.3
Raspberry Pi Zero 2 W Rev 1.0
Raspberry Pi 2 Model B Rev 1.2
Raspberry Pi Compute Module 4 Rev 1.0
Raspberry Pi Compute Module 3 Rev 1.0
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
