3 Commits

Author	SHA1	Message	Date
Lokesh Vutla	97405d843e	ARM: DRA7xx: clocks: Update PLL values ... Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>	2013-06-10 08:43:10 -04:00
Sricharan R	f9b814a8e9	ARM: DRA7xx: Correct the SYS_CLK to 20MHZ ... The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>	2013-06-10 08:43:10 -04:00
Lokesh Vutla	af1d002f89	ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h ... To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>	2013-06-10 08:43:09 -04:00