Use the pinctrl pin offset to get_gpio_mux() to remove the bank num
dependency and instead only use the bank num to assign a bank name.
Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the
pinctrl pin offset typically is aligned to 32.
However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl
pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin
aligned bank num.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Get pinctrl device from gpio-ranges phandle when the property exists,
fallback to get the first pinctrl device.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Implement gpio_request_enable() ops so that the gpio request() ops can
be implemented and a gpio requested pin automatically is pinmuxed for
gpio use, similar to Linux kernel.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add get_pins_count(), get_pin_name() and get_pin_muxing() ops to support
the pinmux status cmd.
=> pinmux dev pinctrl
dev: pinctrl
=> pinmux status
GPIO0_A0 : gpio
GPIO0_A1 : func-1
GPIO0_A2 : gpio
GPIO0_A3 : gpio
GPIO0_A4 : func-1
GPIO0_A5 : gpio
GPIO0_A6 : gpio
GPIO0_A7 : func-1
GPIO0_B0 : gpio
GPIO0_B1 : func-1
GPIO0_B2 : func-1
GPIO0_B3 : gpio
[...]
The change to use ENOENT for unrouted pins also help hide a "Error -22"
message for unrouted pins using the gpio status -a cmd.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a way to get_gpio_mux() based on the pinctrl pin offset, use -1 as
banknum to use the pinctrl pin offset mode instead of bank pin offset.
This mode will be used by the gpio driver to ensure a pin used by gpio
request() and get_function() ops always refer to the same pinctrl pin.
Also add verify_config() of banknum and index to avoid an out of range
access of the pin_banks array, i.e. with gpio6 on rk3066a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a pin_to_bank() helper that can locate a pin bank based on the pin
offset, to be used in get_gpio_mux() and gpio_request_enable() ops.
Reset ctrl->nr_pins to 0 so that pin_to_bank() can locate a bank after
the second probe in U-Boot proper.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Remove the rockchip,rk3399-dwc3 compatible from the dwc3-of-simple
driver now that all boards have changed to use the dwc3-generic driver.
Also remove the amlogic,meson-gxl-dwc3 compatible, it is no longer in
use by any device tree in mainline linux or U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
dev_get_driver_ops() may return NULL when the udevice is invalid.
Move the ops check to top of functions to consistently return -ENOSYS
when ops is unimplemented and prevent trying to access uclass plat data,
also add missing NULL checks to suspend ops.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
(cherry picked from commit 4386ab9118)
On some boards a PMIC regulator is flagged with regulator-on-in-suspend
and does not define any suspend or max microvolt, e.g. on Radxa ROCK 3A:
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
This result in suspend_uV having the value -ENODATA after probe.
This negative voltage, -ENODATA, gets missinterpreted and result in an
unexpected voltage being set by autoset.
E.g. on Radxa ROCK 3A the vcc_ddr regulator by default have a normal and
suspend voltage value of 0.5v. However, due to this missinterpretation
the suspend voltage end up beind set to 0.5625v instead.
Fix this by skip calling regulator_set_suspend_value() in autoset and
also protect calling set value ops when input value is -ENODATA.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
(cherry picked from commit f417c14d88)
Until a live tree is used in U-Boot proper after relocation, use of
ofnode_get_parent() will trigger a call to the very expensive
fdt_parent_offset(), as detailed by the function documentation:
NOTE: This function is expensive, as it must scan the device tree
structure from the start to nodeoffset, *twice*.
Re-use the returned value from a single call instead of having to make
multiple calls for same node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit 6f5b168661)
Until a live tree is used in U-Boot proper after relocation, use of
ofnode_get_parent() will trigger a call to the very expensive
fdt_parent_offset() as detailed by the function documentation:
NOTE: This function is expensive, as it must scan the device tree
structure from the start to nodeoffset, *twice*.
Re-use the returned value from a single call instead of having to make
multiple calls for same node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit 445406afbb)
Use of fdt_parent_offset() is very expensive as detailed by the function
documentation:
NOTE: This function is expensive, as it must scan the device tree
structure from the start to nodeoffset, *twice*.
Re-use the returned value from a single call instead of having to make
multiple calls for same nodeoffset.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit d6330529a5)
The SSCG is active with MDSEL[12] is not set. Previous commit
99c7e03119 ("clk: renesas: rcar-gen3: Replace SSCG caching
with MDSEL/PE caching") inverted the conditional assignment
of priv->sscg = !(cpg_mode & BIT(12)) during conversion from
(priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0;
Invert the assignment back to the correct state.
This fixes R8A77980, R8A77990, R8A77995 and R8A774C0.
Fixes: 99c7e03119 ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Transfer initiation and completion for the non-zero Endpoints are
handled by cdns3_ep_run_transfer() and cdns3_transfer_completed()
respectively.
Failing to flush the cache associated with the TRB Pool within
cdns3_ep_run_transfer() results in the transfers never being initiated.
Similarly, failing to invalidate the cache associated with the TRB pool
within cdns3_transfer_completed() results in the transfers never being
completed.
Fix this.
Fixes: 7e91f6ccdc ("usb: Add Cadence USB3 host and gadget driver")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The buck variable is zero based, i.e. buck=0 match BUCK1 in datasheet.
Remove any buck + 1 calculation to be more consistent in usage of the
buck variable across the different RK8xx variants in the driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Wrong POWER_EN reg is used to get and set enabled state for the RK806
buck 4 and 8 regulators, also wrong POWER_SLP_EN0 bit is used for
suspend state for the RK806 buck 1-8 regulators.
Fix this by not adding one to the zero based buck variable.
Fixes: f172575d92 ("power: rk8xx: add support for RK806")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
In lpddr4_start function error returned by lpddr4_enablepiinitiator
may go undetected due to overwrite of return code.
Add support to handle error in above case.
Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
use dev_dbg() instead of dev_info() for debug related
prints.
Get's rid of below print from console.
"cdns,sierra serdes@5030000: sierra probed"
Signed-off-by: Roger Quadros <rogerq@kernel.org>
With "reg-mux" compatible the driver no longer expects the parent
device to be a syscon type. It uses it's own regmux.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Fix link errors caused by missing Kconfig dependencies:
1. DFU_OVER_USB compiles common/dfu.c which calls g_dnl_clear_detach()
which is implemented in drivers/usb/gadget/g_dnl.c which needs
USB_GADGET_DOWNLOAD. Test case:
$ printf "CONFIG_USB_GADGET_DOWNLOAD=n\nCONFIG_USB_FUNCTION_FASTBOOT=n" \
>>configs/am62px_evm_a53_defconfig
$ make am62px_evm_a53_defconfig
$ make CROSS_COMPILE=aarch64-linux-gnu-
[...]
common/dfu.c:34:(.text.run_usb_dnl_gadget+0x68): undefined reference to `g_dnl_clear_detach
[...]
2. With the above fixed, the same build causes:
common/spl/spl_dfu.c:29:(.text.spl_dfu_cmd+0xb0): undefined reference to `run_usb_dnl_gadget'
This is because SPL_DFU compiles common/spl/spl_dfu.c which calls
run_usb_dnl_gadget() which is implemented in common/dfu.c which needs
DFU_OVER_USB.
Therefore add these dependencies to Kconfig.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Link: https://lore.kernel.org/r/20240910102751.3182982-1-jerome.forissier@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
The current documentation for the bootcount API is on our website and
not the old wiki, update the link in two places.
Signed-off-by: Tom Rini <trini@konsulko.com>
The existing code is unnecessarily convoluted:
Arrays __prci_init_clocks_fu[5|7]40 are initialized with data.
In separate includes fu[5|7]40-prci.h the size of the arrays is provided as
constants.
By moving the structures prci_clk_fu[5|7]40 to the respective code modules
we can directly use ARRAY_SIZE() to access the size of the data used for
initialization.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
If multiple messages are written, line-feeds improve the readability.
Fixes: c40b6df87f ("clk: Add SiFive FU540 PRCI clock driver")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Add device tree compatible string "renesas,rcar-gen4-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen4 DTs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make sure RPC PHY timing registers are configured before performing
bus access. These registers might have been left unconfigured or may
have been configured by a prior stage bootloader and leaving them
unconfigured or misconfigured would interfere with U-Boot operation.
Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment
when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which
makes the interface operate in Serial flash or HyperFlash mode.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make sure DRDRENR register is configured before performing external
address space read. This register might have been configured by a
prior stage bootloader and leaving it unconfigured would interfere
with U-Boot operation. Since U-Boot RPC SPI driver does not support
DDR data transfer mode yet, set this register unconditionally to 0.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Instead of writing DRDMCR with 0 first and then overwriting DRDMCR again
in case any dummy bytes have to be sent out, write DRDMCR in every case
with the amount of dummy bytes that have to be sent out. In case no dummy
bytes have to be sent out, the value written into DRDMCR is zero, so no
dummy bytes are sent out. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Instead of writing DREAR with 0 first and then overwriting DREAR again
in case of 4 byte addressing mode, write DREAR in every case once with
the correct content right away. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add device tree compatible string "renesas,rcar-gen4-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen4 DTs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Please pull the updates for rockchip platform:
- Add board support:
RK3566: Radxa ROCK 3 Model C
Radxa ZERO 3W/3E
Xunlong Orange Pi 3B
RK3568J: Radxa ROCK 3B
RK3308B: Radxa ROCK S0
RK3588: Radxa ROCK 5 ITX
FriendlyElec CM3588 NAS board
- dw-mmc: allow 4-bit mode;
- dts and config updates;
CI:
https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/21997
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Equivalent upstream Linux patch:
690fb3718a70 ("usb: dwc3: Support Synopsys USB 3.1 IP")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Back when the TPM subsystem was refactored tpm_tis_wait_init() ended up
being called after tpm_tis_init() which initializes values the former needs.
Since we added more TPM chipsets since then sitting on an i2c bus, this patch
folds in tpm_tis_wait_init into tpm_tis_init and makes sure it's called in the
right order regardless of the bus the TPM sits on.
The TXFIFO register of LPI2C only has one byte length, and if the length
of the data that needs to be read exceeds 256 bytes, it needs to be
written to TXFIFO multiple times.
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Instead of using the hard-coded bus speed value I2C_SPEED_STANDARD_RATE,
use the actual configured bus speed. This way the bus speed doesn't
change suddenly after calling the imx_lpi2c_probe_chip() function for
example.
Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Newer Samsung SoCs (including newer Exynos, ExynosAuto, Google Tensor)
still use these IPs, or slightly newer versions of it.
Make these drivers available on these platforms by guarding
EXYNOS4/EXYNOS5 specific code behind their configs, and using CCF for
clocks on other platforms.
Tested S3C I2C driver on Exynos7885.
This along with extended clock driver should enable S3C I2C on
Exynos850.
Signed-off-by: David Virag <virag.david003@gmail.com>
Tested-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Heiko Schocher <hs@denx.de>
There is no reason to use goto and just call return. Better is to call
return directly which is done for some if/else parts.
Also make no sense to setup ret to -ETIMEDOUT and then to 0.
Return timeout directly.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
There is no reason to have any pointer to GD that's why remove it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
What model of Radxa ZERO 3W/3E board can be identified using ADC at
runtime, add a Kconfig symbol to allow use of ADC in SPL.
This will be used to identify board model in SPL to allow loading
correct FIT configuration and FDT for U-Boot proper at SPL phase.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Port the RK3308 part of the Rockchip IO Domain driver from linux.
This differs from linux version in that vccio3 iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supply that have been configured.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Hosts capable of 8-bit can also do 4 bits, fix use of 4-bit mode when
8-bit mode is supported.
This fixes use of 1-bit mode with SD NAND on ROCK Pi S using the DT in
v6.11-rc1 that chage to use 8-bit bus to also support eMMC. With this
4-bit mode is used with SD NAND and 8-bit mode with eMMC, same as in
Linux kernel.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix multiplex configuration for PCIe1L0 and PCIe1L1 in PCIESEL_CON for
RK3588 to correctly select between Combo PHYs and PCIe3 PHY.
Currently, the code incorrectly muxes both ports to Combo PHYs,
interfering with PCIe3 PHY settings.
Introduce PHY identifiers to identify the correct Combo PHY and set
the necessary bits accordingly.
This fix is adapted from the upstream Linux commit by Sebastian Reichel:
d16d4002fea6 ("phy: rockchip: naneng-combphy: Fix mux on rk3588")
Fixes: b37260bca1 ("phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
UBI block is an virtual device, that runs on top
of the MTD layer. The blocks are UBI volumes.
Intended to be used in combination with other MTD
drivers.
Despite the fact that it, like mtdblock abstraction,
it used with UCLASS_MTD, they can be used together
on the system without conflicting. For example,
using bcb command:
# Trying to load bcb via mtdblock:
$ bcb load mtd 0 mtd_partition_name
# Trying to load bcb via UBI block:
$ bcb load ubi 1 ubi_volume_name
User always must attach UBI layer (for example, using
ubi_part()) before using UBI block device.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
