GPIO IOMUX control is located at PMU2_IOC or BUS_IOC offset on RK3588.
Based on Linux commit fdc33eba11c5 ("pinctrl/rockchip: add rk3588
support").
Compared to the Linux commit, this include a fix so that the iomux of
GPIO0_B4-D7 is reported correctly.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
GPIO0_C0-C4 iomux is set using PMUGRF_GPIO0C_IOMUX_L reg on RV1126. This
is indicated using the IOMUX_L_SOURCE_PMU flag. Fix reading current mux
by fully adopting the IOMUX_L_SOURCE_PMU related code in Linux kernel.
Based on Linux commit fd4ea48688c6 ("pinctrl: rockchip: Add RV1126
pinctrl support").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
GPIO0_A0-A7 on RK3188 is IOMUX_GPIO_ONLY, however, trying to set gpio
mux return an -ENOTSUPP error code. Fix this by validating using the mux
function type and not the iomux flag.
Based on Linux commit c4a532dee6b6 ("pinctrl: rockchip: handle first
half of rk3188-bank0 correctly").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
For the sake of consistency, make all internal (starting with _)
functions expect a pmic udevice instead of a regulator udevice.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-bob
_ldo_get_suspend_value and _ldo_set_suspend_value get passed the parent
of the regulator (so the pmic) as first argument, therefore this udevice
should be used for pmic_* callbacks instead of using the parent of the
pmic.
To avoid further confusion, let's rename the argument to pmic instead of
dev, highlighting which kind of device we expect as argument.
Fixes: f047e4ab97 ("regulator: rk8xx: add indirection level for some ldo callbacks")
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-bob
Instead of displaying what looks like an error message if a
gpio-reset dt prop is missing for a TPM display a warning that
having a gpio reset on a TPM should not be used for a secure production
device.
TCG TIS spec [1] says:
"The TPM_Init (LRESET#/SPI_RST#) signal MUST be connected to the
platform CPU Reset signal such that it complies with the requirements
specified in section 1.2.7 HOST Platform Reset in the PC Client
Implementation Specification for Conventional BIOS."
The reasoning is that you should not be able to toggle a GPIO and reset
the TPM without resetting the CPU as well because if an attacker can
break into your OS via an OS level security flaw they can then reset the
TPM via GPIO and replay the measurements required to unseal keys
that you have otherwise protected.
Additionally restructure the code for improved readability allowing for
removal of the init label.
Before:
- board with no reset gpio
u-boot=> tpm init && tpm info
tpm_tis_spi_probe: missing reset GPIO
tpm@1 v2.0: VendorID 0x1114, DeviceID 0x3205, RevisionID 0x01 [open]
- board with a reset gpio
u-boot=> tpm init && tpm info
tpm@1 v2.0: VendorID 0x1114, DeviceID 0x3205, RevisionID 0x01 [open]
After:
- board with no reset gpio
u-boot=> tpm init && tpm info
tpm@1 v2.0: VendorID 0x1114, DeviceID 0x3205, RevisionID 0x01 [open]
- board with a reset gpio
u-boot=> tpm init && tpm info
tpm@1: TPM gpio reset should not be used on secure production devices
tpm@1 v2.0: VendorID 0x1114, DeviceID 0x3205, RevisionID 0x01 [open]
[1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
All parts expect the SPLL to run at 702MHz. In U-Boot it's the SPLL_HZ
declaring this rate and in the kernel it's a fixed clock definition.
While everything is expecting 702MHz, the SPLL is not running that
frequency when coming from the bootrom though, instead it's running
at 351MHz and the vendor-u-boot just sets it to the expected frequency.
The SPLL itself is located inside the secure-BUSCRU and in theory
accessible as an SCMI clock, though this requires an unknown amount
of cooperation from trusted-firmware to set at a later stage, though
during the SPL stage we can still access the relevant CRU directly.
The SPLL is for example necessary for the DSI controllers to produce
output.
As the SPLL is "just" another rk3588 pll, just set the desired rate
directly during the SPL stage.
Tested on rk3588-rock5b and rk3588-tiger by reading back the PLL rate
and also observing working DSI output with this change.
Fixes: 6737771600 ("rockchip: rk3588: Add support for sdmmc clocks in SPL")
Suggested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d, reversing
changes made to 2ee6f3a5f7.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
u-boot-dfu-20240516
- Fix cdns3 low power hang via fast access bit
- Multiple dwc3 gadget fixes, mainly for USB support on TI AM6232
- Consistent USB_GADGET_MANUFACTURER for PHYTEC boards
- MAINTAINERS file update for u-boot-dfu
Upstream Linux commit 87dd96111b0b.
When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an endpoint
command.
Current implementation only save and restore GUSB2PHYCFG.SUSPHY
configuration. We must save and clear both GUSB2PHYCFG.ENBLSLPM and
GUSB2PHYCFG.SUSPHY settings. Restore them after the command is
completed.
DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240412202611.3565052-5-alexander.sverdlin@siemens.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Without the NULL check, if the devicetree that u-boot loads does not have a
compatible property then a store access fault will be raised and force the
machine to reset, due to the NULL pointer we passed to strlen. This commit
adds this check and will return -ENOSPC to indicate the get_desc failed.
Signed-off-by: Hanyuan Zhao <zhaohy22@mails.tsinghua.edu.cn>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is disabled by setting DEVDS field. Setting the fast register access
bit ensures that the PHY clock is keeping up in active state.
Therefore, set fast access bit to ensure the accesses to device registers
are quick even in low power states.
commit b5148d946f45 ("usb: cdns3: gadget: set fast access bit") in the
upstream kernel is taken as reference.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240424073911.1943-1-r-gunasekaran@ti.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
MD Danish Anwar <danishanwar@ti.com> says:
This series adds AM64x related compatibles to PRUSS and PRU_RPROC drivers.
This series is a prerequisite for ICSSG Ethernet driver.
Once Support for AM64x is added to PRUSS and PRU_RPROC driver, I'll send
another series to enable ICSSG Ethernet driver for AM64x as well.
Add support for AM64x by adding it's compatible in pruss driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Add support for AM64x PRU cores by adding compatibles for AM64x.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
This driver support the Synopsys Designware Ethernet 10G
IP block refer from the driver dwc_eth_qos.
The driver MAC register mapping is different between
Synopsys QoS IP and Synopsys 10G IP, and thus new file
is created meant for Sysnopsys 10G IP.
The dwc_eth_xgmac_socfpga.c is specific to a device family,
the driver support the specific configuration used in
Intel SoC FPGA Agilex5.
This driver is extensible for other device family to use.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Greg Malysa <greg.malysa@timesys.com> says:
This series adds support for the ADI SC5xx machine type and includes two
core drivers that are required for being able to boot any board--a UART
driver, the gptimer driver which is used as a clock reference (CNTVCNT
is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our
corresponding Linux support relies on u-boot configuring the clocks
correctly before booting, so it is not possible to boot any board
without the CGU/CDU configuration happening here. There are also no
board files, device trees, or defconfigs included here, but some common
definitions that will be used to build board files currently are. The
sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and
sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended
to be a drop-in replacement for the SC594 in terms of peripherals, with
a Cortex-A55 instead.
Some of the configuration code in dmcinit and clkinit is quite scary and
causes a lot of checkpatch violations. It is modified from code
initially provided by ADI, but it has not been fully rewritten. There's
a question of how important it is to clean up this code--it has some
quality violations, but it has been in use (including in production) for
over two years and is known to work for performing the low level SoC
initialization, while a rewrite might introduce timing or sequence bugs
that could take a significant amount of time to detect in the future.
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
