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53 Commits

Author SHA1 Message Date
Patrick Delaunay
938e0e3f6e clock: stm32mp1: add stgen clock source change support 
The STGEN is the clock source for the Cortex A7 arch timer.
So after modification of its frequency, CP15 cntfreq is updated
and a new timer init is performed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2018-04-06 20:45:28 -04:00
Patrick Delaunay
266fa4df00 clk: stm32mp1: add clock tree initialization 
add binding and code for clock tree initialization from device tree

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2018-03-19 16:14:22 -04:00
Patrick Delaunay
a6151916cb clk: add driver for stm32mp1 
add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
  of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2018-03-19 16:14:22 -04:00