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arm: am437x: Enable hardware leveling for EMIF

Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values.  Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.

Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
James Doublesin
2014-12-22 16:26:11 -06:00
committed by Tom Rini
parent e2a6207bcc
commit fc46bae2ae
7 changed files with 138 additions and 207 deletions

View File

@@ -650,8 +650,8 @@ struct emif_reg_struct {
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
u32 padding9[6];
u32 emif_ddr_phy_status[21];
u32 padding10[27];
u32 emif_ddr_phy_status[28];
u32 padding10[20];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@@ -700,9 +700,36 @@ struct emif_reg_struct {
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
u32 padding[22];
u32 emif_ddr_fifo_misaligned_clear_1;
u32 emif_ddr_fifo_misaligned_clear_2;
u32 emif_ddr_ext_phy_ctrl_25;
u32 emif_ddr_ext_phy_ctrl_25_shdw;
u32 emif_ddr_ext_phy_ctrl_26;
u32 emif_ddr_ext_phy_ctrl_26_shdw;
u32 emif_ddr_ext_phy_ctrl_27;
u32 emif_ddr_ext_phy_ctrl_27_shdw;
u32 emif_ddr_ext_phy_ctrl_28;
u32 emif_ddr_ext_phy_ctrl_28_shdw;
u32 emif_ddr_ext_phy_ctrl_29;
u32 emif_ddr_ext_phy_ctrl_29_shdw;
u32 emif_ddr_ext_phy_ctrl_30;
u32 emif_ddr_ext_phy_ctrl_30_shdw;
u32 emif_ddr_ext_phy_ctrl_31;
u32 emif_ddr_ext_phy_ctrl_31_shdw;
u32 emif_ddr_ext_phy_ctrl_32;
u32 emif_ddr_ext_phy_ctrl_32_shdw;
u32 emif_ddr_ext_phy_ctrl_33;
u32 emif_ddr_ext_phy_ctrl_33_shdw;
u32 emif_ddr_ext_phy_ctrl_34;
u32 emif_ddr_ext_phy_ctrl_34_shdw;
u32 emif_ddr_ext_phy_ctrl_35;
u32 emif_ddr_ext_phy_ctrl_35_shdw;
union {
u32 emif_ddr_ext_phy_ctrl_36;
u32 emif_ddr_fifo_misaligned_clear_1;
};
union {
u32 emif_ddr_ext_phy_ctrl_36_shdw;
u32 emif_ddr_fifo_misaligned_clear_2;
};
};
struct dmm_lisa_map_regs {