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mx6: clock: Introduce disable_ipu_clock()

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Introduce disable_ipu_clock(). This is done in preparation for
configuring the NoC registers on i.MX6QP in SPL.

Afer the NoC registers are set the IPU clocks can be disabled.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Fabio Estevam
2019-07-12 09:32:23 -03:00
committed by Stefano Babic
parent 1be51fed56
commit fa64df4602
2 changed files with 13 additions and 0 deletions
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1
arch/arm/include/asm/arch-mx6/clock.h
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@@ -71,6 +71,7 @@ int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num); int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void); void enable_ipu_clock(void);
void disable_ipu_clock(void);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable); void enable_enet_clk(unsigned char enable);
int enable_lcdif_clock(u32 base_addr, bool enable); int enable_lcdif_clock(u32 base_addr, bool enable);

12
arch/arm/mach-imx/mx6/clock.c
View File

@@ -1287,6 +1287,18 @@ void enable_ipu_clock(void)
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
} }
} }
void disable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
if (is_mx6dqp()) {
clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
}
}
#endif #endif
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD