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configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig
Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py. Kconfig uses a choice between the 3 values supported in U-Boot, including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK (the default configuration). The patch also avoids to select simultaneously 2 configurations. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
committed by
Tom Rini
parent
e7882f65f0
commit
f8dc7f2f18
@@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE
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default 64 if SYS_CACHE_SHIFT_6
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default 64 if SYS_CACHE_SHIFT_6
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default 32 if SYS_CACHE_SHIFT_5
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default 32 if SYS_CACHE_SHIFT_5
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choice
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prompt "Select the ARM data write cache policy"
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default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
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TARGET_BCMNSP || CPU_PXA || RZA1
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default SYS_ARM_CACHE_WRITEBACK
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config SYS_ARM_CACHE_WRITEBACK
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bool "Write-back (WB)"
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help
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A write updates the cache only and marks the cache line as dirty.
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External memory is updated only when the line is evicted or explicitly
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cleaned.
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config SYS_ARM_CACHE_WRITETHROUGH
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bool "Write-through (WT)"
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help
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A write updates both the cache and the external memory system.
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This does not mark the cache line as dirty.
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config SYS_ARM_CACHE_WRITEALLOC
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bool "Write allocation (WA)"
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help
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A cache line is allocated on a write miss. This means that executing a
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store instruction on the processor might cause a burst read to occur.
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There is a linefill to obtain the data for the cache line, before the
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write is performed.
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endchoice
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config ARCH_CPU_INIT
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config ARCH_CPU_INIT
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bool "Enable ARCH_CPU_INIT"
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bool "Enable ARCH_CPU_INIT"
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help
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help
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@@ -10,7 +10,6 @@
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/* Architecture, CPU, chip, etc */
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/* Architecture, CPU, chip, etc */
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#define CONFIG_IPROC
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#define CONFIG_IPROC
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#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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/* Memory Info */
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/* Memory Info */
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#define CONFIG_SYS_SDRAM_BASE 0x61000000
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#define CONFIG_SYS_SDRAM_BASE 0x61000000
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@@ -16,7 +16,6 @@
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/* Miscellaneous */
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/* Miscellaneous */
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_TAG
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/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
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/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
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@@ -8,8 +8,6 @@
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#ifndef __CONFIG_PXA_COMMON_H__
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#ifndef __CONFIG_PXA_COMMON_H__
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#define __CONFIG_PXA_COMMON_H__
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#define __CONFIG_PXA_COMMON_H__
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#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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/*
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/*
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* KGDB
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* KGDB
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*/
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*/
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@@ -1770,7 +1770,6 @@ CONFIG_SYS_AMASK4
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CONFIG_SYS_AMASK5
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CONFIG_SYS_AMASK5
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CONFIG_SYS_AMASK6
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CONFIG_SYS_AMASK6
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CONFIG_SYS_AMASK7
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CONFIG_SYS_AMASK7
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CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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CONFIG_SYS_AT91_CPU_NAME
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CONFIG_SYS_AT91_CPU_NAME
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CONFIG_SYS_AT91_MAIN_CLOCK
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CONFIG_SYS_AT91_MAIN_CLOCK
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CONFIG_SYS_AT91_PLLA
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CONFIG_SYS_AT91_PLLA
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