powerpc: Enable device tree support for MPC8548CDS

Add device tree for MPC8548CDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

arch/powerpc/dts/Makefile

@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
 dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
 dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
 dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb

arch/powerpc/dts/mpc8548-post.dtsi

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,mpc8548-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+};

arch/powerpc/dts/mpc8548.dtsi

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8548@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+};

arch/powerpc/dts/mpc8548cds.dts

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Device Tree Source
+ *
+ * Copyright 2006 - 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+	model = "fsl,MPC8548CDS";
+	compatible = "fsl,MPC8548CDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc8548@e0000000 {
+		ranges = <0x0 0x0 0xe0000000 0x100000>;
+	};
+};
+
+/include/ "mpc8548-post.dtsi"

arch/powerpc/dts/mpc8548cds_36b.dts

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS (36-bit address map) Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+	model = "fsl,MPC8548CDS";
+	compatible = "fsl,MPC8548CDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc8548@fe0000000 {
+		ranges = <0x0 0xf 0xe0000000 0x100000>;
+	};
+};
+
+/include/ "mpc8548-post.dtsi"

configs/MPC8548CDS_36BIT_defconfig

@@ -1,8 +1,11 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF80000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
+CONFIG_OF_CONTROL=y
 CONFIG_PHYS_64BIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

configs/MPC8548CDS_defconfig

@@ -1,8 +1,11 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF80000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=10

configs/MPC8548CDS_legacy_defconfig

@@ -1,8 +1,11 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF80000
 CONFIG_MPC85xx=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_OF_CONTROL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"