dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-11-01 19:05:51 +01:00
Code Issues Packages Projects Releases Wiki Activity

spi: zynq_[q]spi: Convert config's to macro's

Browse Source 
Remove below config options and convert them to macros. They have never
been configured to different values than default one. And also it makes
sense to reduce the config_whitelist.
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_XILINX_SPI_IDLE_VAL

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ashok Reddy Soma
2020-05-18 01:11:00 -06:00
committed by Michal Simek
parent 26e62cc971
commit f44bd3bcfd
4 changed files with 6 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/spi/xilinx_spi.c
View File

@@ -76,9 +76,7 @@
SPICR_SPE)
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#endif
#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
@@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
i < priv->fifo_depth) {
d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
debug("spi_xfer: tx:%x ", d);
/* write out and wait for processing (receive data) */
writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);