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Watchdog: introduce ARM SBSA watchdog driver

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According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal
(WS0) is for alerting the system by interrupt, the second one (WS1) is a
real hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)

This driver can operate ARM SBSA Generic Watchdog as a single stage
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Zhao Qiang
2020-07-10 16:55:18 +08:00
committed by Priyanka Jain
parent ed188aa886
commit f27d73e941
4 changed files with 142 additions and 0 deletions
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@@ -689,6 +689,7 @@ M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
I2C
M: Heiko Schocher <hs@denx.de>