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driver/ddr/fsl: Add support of overriding chip select write leveling

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JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2014-09-05 13:52:43 +08:00
parent 5cb27c5d44
commit ef87cab664
3 changed files with 7 additions and 0 deletions
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2
drivers/ddr/fsl/interactive.c
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@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),