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https://xff.cz/git/u-boot/
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clk: rockchip: Add clocks used by VOP and mipi-dsi on rk3399
These need to be handled for VOP/MIPI-DSI support. Signed-off-by: Ondrej Jirman <megi@xff.cz>
This commit is contained in:
@@ -1002,6 +1002,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
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case PCLK_WDT:
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case PCLK_WDT:
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rate = rk3399_alive_get_clk(priv->cru);
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rate = rk3399_alive_get_clk(priv->cru);
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break;
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break;
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case SCLK_DPHY_PLL:
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return 24000000;
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default:
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default:
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log_debug("Unknown clock %lu\n", clk->id);
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log_debug("Unknown clock %lu\n", clk->id);
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return -ENOENT;
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return -ENOENT;
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@@ -1065,6 +1067,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
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case DCLK_VOP1:
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case DCLK_VOP1:
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ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
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ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
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break;
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break;
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case ACLK_VOP0:
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case HCLK_VOP0:
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case ACLK_VOP1:
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case ACLK_VOP1:
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case HCLK_VOP1:
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case HCLK_VOP1:
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case HCLK_SD:
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case HCLK_SD:
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@@ -1169,6 +1173,11 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
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return rk3399_gmac_set_parent(clk, parent);
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return rk3399_gmac_set_parent(clk, parent);
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case SCLK_PCIEPHY_REF:
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case SCLK_PCIEPHY_REF:
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return rk3399_pciephy_set_parent(clk, parent);
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return rk3399_pciephy_set_parent(clk, parent);
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case DCLK_VOP1_DIV:
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case DCLK_VOP0_DIV:
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case DCLK_VOP1:
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case DCLK_VOP0:
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return 0;
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}
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}
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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@@ -1262,6 +1271,12 @@ static int rk3399_clk_enable(struct clk *clk)
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if (readl(&priv->cru->clksel_con[18]) & BIT(10))
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if (readl(&priv->cru->clksel_con[18]) & BIT(10))
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rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
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rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
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break;
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break;
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case SCLK_DPHY_TX0_CFG:
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rk_clrreg(&priv->cru->clkgate_con[21], BIT(1));
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break;
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case PCLK_VIO_GRF:
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rk_clrreg(&priv->cru->clkgate_con[29], BIT(12));
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break;
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default:
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default:
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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return -ENOENT;
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return -ENOENT;
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@@ -1357,6 +1372,12 @@ static int rk3399_clk_disable(struct clk *clk)
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if (readl(&priv->cru->clksel_con[18]) & BIT(10))
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if (readl(&priv->cru->clksel_con[18]) & BIT(10))
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rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
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rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
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break;
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break;
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case SCLK_DPHY_TX0_CFG:
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rk_setreg(&priv->cru->clkgate_con[21], BIT(1));
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break;
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case PCLK_VIO_GRF:
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rk_setreg(&priv->cru->clkgate_con[29], BIT(12));
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break;
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default:
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default:
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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debug("%s: unsupported clk %ld\n", __func__, clk->id);
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return -ENOENT;
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return -ENOENT;
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