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arm: mach-snapdragon: pinctrl: clarify gpio disable bit

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The TLMM_GPIO_ENABLE bit is actually use to disable
the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
This commit is contained in:
Ramon Fried
2019-01-12 11:47:27 +02:00
committed by Tom Rini
parent b1cd785755
commit ea7bf8fb08
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-snapdragon/pinctrl-snapdragon.c
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@@ -22,7 +22,7 @@ struct msm_pinctrl_priv {
#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
#define TLMM_GPIO_ENABLE BIT(9) #define TLMM_GPIO_DISABLE BIT(9)
static const struct pinconf_param msm_conf_params[] = { static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
@@ -74,7 +74,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
struct msm_pinctrl_priv *priv = dev_get_priv(dev); struct msm_pinctrl_priv *priv = dev_get_priv(dev);
clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE, TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
priv->data->get_function_mux(func_selector) << 2); priv->data->get_function_mux(func_selector) << 2);
return 0; return 0;
} }