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arch/arm: add SEC JR0 offset

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Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Alex Porosanu
2016-04-29 15:17:58 +03:00
committed by York Sun
parent 56747bfdbd
commit e99d719359
5 changed files with 28 additions and 10 deletions
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8
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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@@ -77,8 +77,12 @@
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)