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mtd: nand: denali: fix unaligned cache operations on ARMv7 SoCs

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If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".

=> nand info

Device 0: nand0, sector size 256 KiB
  Page size       4096 b
  OOB size         224 b
  Erase size    262144 b
  subpagesize     4096 b
  options     0x00104200
  bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
  ...

The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]
This commit is contained in:
Masahiro Yamada
2018-09-10 11:17:30 +09:00
committed by Tom Rini
parent f850371997
commit e8f65763ef
1 changed files with 4 additions and 0 deletions
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4
drivers/mtd/nand/denali.c
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@@ -21,6 +21,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
{ {
unsigned long addr = (unsigned long)ptr; unsigned long addr = (unsigned long)ptr;
size = ALIGN(size, ARCH_DMA_MINALIGN);
if (dir == DMA_FROM_DEVICE) if (dir == DMA_FROM_DEVICE)
invalidate_dcache_range(addr, addr + size); invalidate_dcache_range(addr, addr + size);
else else
@@ -32,6 +34,8 @@ static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size, static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
enum dma_data_direction dir) enum dma_data_direction dir)
{ {
size = ALIGN(size, ARCH_DMA_MINALIGN);
if (dir != DMA_TO_DEVICE) if (dir != DMA_TO_DEVICE)
invalidate_dcache_range(addr, addr + size); invalidate_dcache_range(addr, addr + size);
} }