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dts: stm32mp1: clock tree update

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- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay
2019-01-30 13:07:05 +01:00
committed by Tom Rini
parent 8d6310aa0b
commit e74b74c528
2 changed files with 15 additions and 15 deletions
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3
include/dt-bindings/clock/stm32mp1-clks.h
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@@ -248,7 +248,4 @@
#define STM32MP1_LAST_CLK 232
#define LTDC_K LTDC_PX
#define ETHMAC_K ETHCK_K
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */