Merge git://git.denx.de/u-boot-uniphier

- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups

drivers/clk/uniphier/Makefile

@@ -1,2 +1,3 @@
 obj-y	+= clk-uniphier-core.o
+obj-y	+= clk-uniphier-sys.o
 obj-y	+= clk-uniphier-mio.o

drivers/clk/uniphier/clk-uniphier-core.c

@@ -146,6 +146,36 @@ static int uniphier_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_clk_match[] = {
+	/* System clock */
+	{
+		.compatible = "socionext,uniphier-ld4-clock",
+		.data = (ulong)&uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-clock",
+		.data = (ulong)&uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-clock",
+		.data = (ulong)&uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-clock",
+		.data = (ulong)&uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-clock",
+		.data = (ulong)&uniphier_pxs2_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-clock",
+		.data = (ulong)&uniphier_ld20_sys_clk_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-clock",
+		.data = (ulong)&uniphier_ld20_sys_clk_data,
+	},
+	/* Media I/O clock */
 	{
 		.compatible = "socionext,uniphier-ld4-mio-clock",
 		.data = (ulong)&uniphier_mio_clk_data,

drivers/clk/uniphier/clk-uniphier-sys.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "clk-uniphier.h"
+
+const struct uniphier_clk_gate_data uniphier_pxs2_sys_clk_gate[] = {
+	UNIPHIER_CLK_GATE(8, 0x2104, 10),	/* stdmac */
+	UNIPHIER_CLK_GATE(12, 0x2104, 6),	/* gio (Pro4, Pro5) */
+	UNIPHIER_CLK_GATE(14, 0x2104, 16),	/* usb30 (Pro4, Pro5, PXs2) */
+	UNIPHIER_CLK_GATE(15, 0x2104, 17),	/* usb31 (Pro4, Pro5, PXs2) */
+	UNIPHIER_CLK_GATE(16, 0x2104, 19),	/* usb30-phy (PXs2) */
+	UNIPHIER_CLK_GATE(20, 0x2104, 20),	/* usb31-phy (PXs2) */
+	UNIPHIER_CLK_END
+};
+
+const struct uniphier_clk_data uniphier_pxs2_sys_clk_data = {
+	.gate = uniphier_pxs2_sys_clk_gate,
+};
+
+const struct uniphier_clk_gate_data uniphier_ld20_sys_clk_gate[] = {
+	UNIPHIER_CLK_GATE(8, 0x210c, 8),	/* stdmac */
+	UNIPHIER_CLK_GATE(14, 0x210c, 14),	/* usb30 (LD20) */
+	UNIPHIER_CLK_GATE(16, 0x210c, 12),	/* usb30-phy0 (LD20) */
+	UNIPHIER_CLK_GATE(17, 0x210c, 13),	/* usb30-phy1 (LD20) */
+	UNIPHIER_CLK_END
+};
+
+const struct uniphier_clk_data uniphier_ld20_sys_clk_data = {
+	.gate = uniphier_ld20_sys_clk_gate,
+};

drivers/clk/uniphier/clk-uniphier.h

@@ -50,6 +50,8 @@ struct uniphier_clk_data {
 		.rates = {(_reg),},			\
 	}
 
+extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data;
+extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data;
 extern const struct uniphier_clk_data uniphier_mio_clk_data;
 
 #endif /* __CLK_UNIPHIER_H__ */

drivers/core/ofnode.c

@@ -627,3 +627,15 @@ int ofnode_read_resource(ofnode node, uint index, struct resource *res)
 		return 0;
 	}
 }
+
+int ofnode_read_resource_byname(ofnode node, const char *name,
+				struct resource *res)
+{
+	int index;
+
+	index = ofnode_stringlist_search(node, "reg-names", name);
+	if (index < 0)
+		return index;
+
+	return ofnode_read_resource(node, index, res);
+}

drivers/core/read.c

@@ -164,3 +164,9 @@ int dev_read_resource(struct udevice *dev, uint index, struct resource *res)
 {
 	return ofnode_read_resource(dev_ofnode(dev), index, res);
 }
+
+int dev_read_resource_byname(struct udevice *dev, const char *name,
+			     struct resource *res)
+{
+	return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
+}

drivers/mtd/nand/Kconfig

@@ -16,6 +16,13 @@ config NAND_DENALI
 	help
 	  Enable support for the Denali NAND controller.
 
+config NAND_DENALI_DT
+	bool "Support Denali NAND controller as a DT device"
+	depends on NAND_DENALI && OF_CONTROL && DM
+	help
+	  Enable the driver for NAND flash on platforms using a Denali NAND
+	  controller as a DT device.
+
 config SYS_NAND_DENALI_64BIT
 	bool "Use 64-bit variant of Denali NAND controller"
 	depends on NAND_DENALI

drivers/mtd/nand/Makefile

@@ -44,6 +44,7 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 obj-$(CONFIG_NAND_DENALI) += denali.o
+obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o

drivers/mtd/nand/denali.c

@@ -1175,7 +1175,7 @@ static void denali_hw_init(struct denali_nand_info *denali)
 
 static struct nand_ecclayout nand_oob;
 
-static int denali_init(struct denali_nand_info *denali)
+int denali_init(struct denali_nand_info *denali)
 {
 	struct mtd_info *mtd = nand_to_mtd(&denali->nand);
 	int ret;
@@ -1273,6 +1273,7 @@ fail:
 	return ret;
 }
 
+#ifndef CONFIG_NAND_DENALI_DT
 static int __board_nand_init(void)
 {
 	struct denali_nand_info *denali;
@@ -1296,3 +1297,4 @@ void board_nand_init(void)
 	if (__board_nand_init() < 0)
 		pr_warn("Failed to initialize Denali NAND controller.\n");
 }
+#endif

drivers/mtd/nand/denali.h

@@ -464,4 +464,6 @@ struct denali_nand_info {
 	uint32_t max_banks;
 };
 
+int denali_init(struct denali_nand_info *denali);
+
 #endif /* __DENALI_H__ */

drivers/mtd/nand/denali_dt.c

@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include "denali.h"
+
+static const struct udevice_id denali_nand_dt_ids[] = {
+	{
+		.compatible = "altr,socfpga-denali-nand",
+	},
+	{
+		.compatible = "socionext,uniphier-denali-nand-v5a",
+	},
+	{
+		.compatible = "socionext,uniphier-denali-nand-v5b",
+	},
+	{ /* sentinel */ }
+};
+
+static int denali_dt_probe(struct udevice *dev)
+{
+	struct denali_nand_info *denali = dev_get_priv(dev);
+	struct resource res;
+	int ret;
+
+	ret = dev_read_resource_byname(dev, "denali_reg", &res);
+	if (ret)
+		return ret;
+
+	denali->flash_reg = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = dev_read_resource_byname(dev, "nand_data", &res);
+	if (ret)
+		return ret;
+
+	denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res));
+
+	return denali_init(denali);
+}
+
+U_BOOT_DRIVER(denali_nand_dt) = {
+	.name = "denali-nand-dt",
+	.id = UCLASS_MISC,
+	.of_match = denali_nand_dt_ids,
+	.probe = denali_dt_probe,
+	.priv_auto_alloc_size = sizeof(struct denali_nand_info),
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_GET_DRIVER(denali_nand_dt),
+					  &dev);
+	if (ret && ret != -ENODEV)
+		printf("Failed to initialize Denali NAND controller. (error %d)\n",
+		       ret);
+}

drivers/reset/reset-uniphier.c

@@ -77,6 +77,17 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
 	UNIPHIER_RESET_END,
 };
 
+static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
+	UNIPHIER_RESETX(2, 0x200c, 0),		/* NAND */
+	UNIPHIER_RESETX(4, 0x200c, 2),		/* eMMC */
+	UNIPHIER_RESETX(8, 0x200c, 12),		/* STDMAC */
+	UNIPHIER_RESETX(12, 0x200c, 5),		/* USB30 (GIO0) */
+	UNIPHIER_RESETX(13, 0x200c, 6),		/* USB31 (GIO1) */
+	UNIPHIER_RESETX(16, 0x200c, 16),	/* USB30-PHY */
+	UNIPHIER_RESETX(20, 0x200c, 17),	/* USB31-PHY */
+	UNIPHIER_RESET_END,
+};
+
 /* Media I/O reset data */
 #define UNIPHIER_MIO_RESET_SD(id, ch)			\
 	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
@@ -268,6 +279,10 @@ static const struct udevice_id uniphier_reset_match[] = {
 		.compatible = "socionext,uniphier-ld20-reset",
 		.data = (ulong)uniphier_ld20_sys_reset_data,
 	},
+	{
+		.compatible = "socionext,uniphier-pxs3-reset",
+		.data = (ulong)uniphier_pxs3_sys_reset_data,
+	},
 	/* Media I/O reset */
 	{
 		.compatible = "socionext,uniphier-ld4-mio-reset",
@@ -294,7 +309,15 @@ static const struct udevice_id uniphier_reset_match[] = {
 		.data = (ulong)uniphier_mio_reset_data,
 	},
 	{
-		.compatible = "socionext,uniphier-ld20-mio-reset",
+		.compatible = "socionext,uniphier-ld11-sd-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-sd-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs3-sd-reset",
 		.data = (ulong)uniphier_mio_reset_data,
 	},
 	/* Peripheral reset */
@@ -326,6 +349,10 @@ static const struct udevice_id uniphier_reset_match[] = {
 		.compatible = "socionext,uniphier-ld20-peri-reset",
 		.data = (ulong)uniphier_pro4_peri_reset_data,
 	},
+	{
+		.compatible = "socionext,uniphier-pxs3-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
 	{ /* sentinel */ }
 };