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imx: mx35: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau
committed by
Stefano Babic
Stefano Babic
parent
8342cc37aa
commit
e2003c16c0
@@ -29,7 +29,6 @@ LIB = $(obj)lib$(SOC).o
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COBJS += generic.o
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COBJS += timer.o
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COBJS += iomux.o
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COBJS += mx35_sdram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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@@ -1,114 +0,0 @@
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx35_pins.h>
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#include <asm/arch/iomux.h>
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/*
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* IOMUX register (base) addresses
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*/
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enum iomux_reg_addr {
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IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */
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IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
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IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
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IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
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IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x7A4, /* last Pad control */
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IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7A8, /* input select */
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IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
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};
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#define MUX_PIN_NUM_MAX \
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(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
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#define MUX_INPUT_NUM_MUX \
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(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
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/*
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* Request ownership for an IO pin. This function has to be the first one
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* being called before that pin is used.
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*/
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void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
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{
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u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
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if (mux_reg != NON_MUX_I) {
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mux_reg += IOMUXGPR;
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writel(cfg, mux_reg);
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}
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}
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/*
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* Release ownership for an IO pin
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*/
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void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
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{
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}
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/*
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* This function configures the pad value for a IOMUX pin.
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*
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* @param pin a pin number as defined in iomux_pin_name_t
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* @param config the ORed value of elements defined in iomux_pad_config_t
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*/
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void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
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{
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u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
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writel(config, pad_reg);
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}
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/*
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* This function enables/disables the general purpose function for a particular
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* signal.
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*
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* @param gp one signal as defined in iomux_gp_func_t
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* @param en enable/disable
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*/
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void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
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{
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u32 l;
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l = readl(IOMUXGPR);
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if (en)
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l |= gp;
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else
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l &= ~gp;
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writel(l, IOMUXGPR);
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}
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/*
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* This function configures input path.
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*
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* @param input index of input select register as defined in
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* iomux_input_select_t
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* @param config the binary value of elements defined in
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* iomux_input_config_t
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*/
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void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
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{
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u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
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writel(config, reg);
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}
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@@ -1,296 +0,0 @@
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/*
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* (C) Copyright 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MACH_MX35_IOMUX_H__
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#define __MACH_MX35_IOMUX_H__
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#include <asm/arch/imx-regs.h>
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/*
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* various IOMUX functions
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*/
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typedef enum iomux_pin_config {
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MUX_CONFIG_FUNC = 0, /* used as function */
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MUX_CONFIG_ALT1, /* used as alternate function 1 */
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MUX_CONFIG_ALT2, /* used as alternate function 2 */
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MUX_CONFIG_ALT3, /* used as alternate function 3 */
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MUX_CONFIG_ALT4, /* used as alternate function 4 */
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MUX_CONFIG_ALT5, /* used as alternate function 5 */
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MUX_CONFIG_ALT6, /* used as alternate function 6 */
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MUX_CONFIG_ALT7, /* used as alternate function 7 */
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MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */
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MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */
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} iomux_pin_cfg_t;
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/*
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* various IOMUX pad functions
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*/
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typedef enum iomux_pad_config {
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PAD_CTL_DRV_3_3V = 0x0 << 13,
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PAD_CTL_DRV_1_8V = 0x1 << 13,
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PAD_CTL_HYS_CMOS = 0x0 << 8,
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PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
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PAD_CTL_PKE_NONE = 0x0 << 7,
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PAD_CTL_PKE_ENABLE = 0x1 << 7,
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PAD_CTL_PUE_KEEPER = 0x0 << 6,
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PAD_CTL_PUE_PUD = 0x1 << 6,
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PAD_CTL_100K_PD = 0x0 << 4,
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PAD_CTL_47K_PU = 0x1 << 4,
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PAD_CTL_100K_PU = 0x2 << 4,
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PAD_CTL_22K_PU = 0x3 << 4,
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PAD_CTL_ODE_CMOS = 0x0 << 3,
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PAD_CTL_ODE_OpenDrain = 0x1 << 3,
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PAD_CTL_DRV_NORMAL = 0x0 << 1,
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PAD_CTL_DRV_HIGH = 0x1 << 1,
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PAD_CTL_DRV_MAX = 0x2 << 1,
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PAD_CTL_SRE_SLOW = 0x0 << 0,
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PAD_CTL_SRE_FAST = 0x1 << 0
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} iomux_pad_config_t;
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/*
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* various IOMUX general purpose functions
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*/
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typedef enum iomux_gp_func {
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MUX_SDCTL_CSD0_SEL = 0x1 << 0,
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MUX_SDCTL_CSD1_SEL = 0x1 << 1,
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MUX_TAMPER_DETECT_EN = 0x1 << 2,
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} iomux_gp_func_t;
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/*
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* various IOMUX input select register index
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*/
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typedef enum iomux_input_select {
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MUX_IN_AMX_P5_RXCLK = 0,
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MUX_IN_AMX_P5_RXFS,
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MUX_IN_AMX_P6_DA,
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MUX_IN_AMX_P6_DB,
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MUX_IN_AMX_P6_RXCLK,
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MUX_IN_AMX_P6_RXFS,
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MUX_IN_AMX_P6_TXCLK,
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MUX_IN_AMX_P6_TXFS,
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MUX_IN_CAN1_CANRX,
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MUX_IN_CAN2_CANRX,
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MUX_IN_CCM_32K_MUXED,
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MUX_IN_CCM_PMIC_RDY,
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MUX_IN_CSPI1_SS2_B,
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MUX_IN_CSPI1_SS3_B,
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MUX_IN_CSPI2_CLK_IN,
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MUX_IN_CSPI2_DATAREADY_B,
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MUX_IN_CSPI2_MISO,
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MUX_IN_CSPI2_MOSI,
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MUX_IN_CSPI2_SS0_B,
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MUX_IN_CSPI2_SS1_B,
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MUX_IN_CSPI2_SS2_B,
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MUX_IN_CSPI2_SS3_B,
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MUX_IN_EMI_WEIM_DTACK_B,
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MUX_IN_ESDHC1_DAT4_IN,
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MUX_IN_ESDHC1_DAT5_IN,
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MUX_IN_ESDHC1_DAT6_IN,
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MUX_IN_ESDHC1_DAT7_IN,
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MUX_IN_ESDHC3_CARD_CLK_IN,
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MUX_IN_ESDHC3_CMD_IN,
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MUX_IN_ESDHC3_DAT0,
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MUX_IN_ESDHC3_DAT1,
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MUX_IN_ESDHC3_DAT2,
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MUX_IN_ESDHC3_DAT3,
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MUX_IN_GPIO1_IN_0,
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MUX_IN_GPIO1_IN_10,
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MUX_IN_GPIO1_IN_11,
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MUX_IN_GPIO1_IN_1,
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MUX_IN_GPIO1_IN_20,
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MUX_IN_GPIO1_IN_21,
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MUX_IN_GPIO1_IN_22,
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MUX_IN_GPIO1_IN_2,
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MUX_IN_GPIO1_IN_3,
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MUX_IN_GPIO1_IN_4,
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MUX_IN_GPIO1_IN_5,
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MUX_IN_GPIO1_IN_6,
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MUX_IN_GPIO1_IN_7,
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MUX_IN_GPIO1_IN_8,
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MUX_IN_GPIO1_IN_9,
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MUX_IN_GPIO2_IN_0,
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MUX_IN_GPIO2_IN_10,
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MUX_IN_GPIO2_IN_11,
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MUX_IN_GPIO2_IN_12,
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MUX_IN_GPIO2_IN_13,
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MUX_IN_GPIO2_IN_14,
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MUX_IN_GPIO2_IN_15,
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MUX_IN_GPIO2_IN_16,
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MUX_IN_GPIO2_IN_17,
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MUX_IN_GPIO2_IN_18,
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MUX_IN_GPIO2_IN_19,
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MUX_IN_GPIO2_IN_1,
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MUX_IN_GPIO2_IN_20,
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MUX_IN_GPIO2_IN_21,
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MUX_IN_GPIO2_IN_22,
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MUX_IN_GPIO2_IN_23,
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MUX_IN_GPIO2_IN_24,
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MUX_IN_GPIO2_IN_25,
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MUX_IN_GPIO2_IN_26,
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MUX_IN_GPIO2_IN_27,
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MUX_IN_GPIO2_IN_28,
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MUX_IN_GPIO2_IN_29,
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MUX_IN_GPIO2_IN_2,
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MUX_IN_GPIO2_IN_30,
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MUX_IN_GPIO2_IN_31,
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MUX_IN_GPIO2_IN_3,
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MUX_IN_GPIO2_IN_4,
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MUX_IN_GPIO2_IN_5,
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MUX_IN_GPIO2_IN_6,
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MUX_IN_GPIO2_IN_7,
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MUX_IN_GPIO2_IN_8,
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MUX_IN_GPIO2_IN_9,
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MUX_IN_GPIO3_IN_0,
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MUX_IN_GPIO3_IN_10,
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MUX_IN_GPIO3_IN_11,
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MUX_IN_GPIO3_IN_12,
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MUX_IN_GPIO3_IN_13,
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MUX_IN_GPIO3_IN_14,
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MUX_IN_GPIO3_IN_15,
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MUX_IN_GPIO3_IN_4,
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MUX_IN_GPIO3_IN_5,
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MUX_IN_GPIO3_IN_6,
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MUX_IN_GPIO3_IN_7,
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MUX_IN_GPIO3_IN_8,
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MUX_IN_GPIO3_IN_9,
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MUX_IN_I2C3_SCL_IN,
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MUX_IN_I2C3_SDA_IN,
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MUX_IN_IPU_DISPB_D0_VSYNC,
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MUX_IN_IPU_DISPB_D12_VSYNC,
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MUX_IN_IPU_DISPB_SD_D,
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MUX_IN_IPU_SENSB_DATA_0,
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MUX_IN_IPU_SENSB_DATA_1,
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MUX_IN_IPU_SENSB_DATA_2,
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MUX_IN_IPU_SENSB_DATA_3,
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MUX_IN_IPU_SENSB_DATA_4,
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MUX_IN_IPU_SENSB_DATA_5,
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MUX_IN_IPU_SENSB_DATA_6,
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MUX_IN_IPU_SENSB_DATA_7,
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MUX_IN_KPP_COL_0,
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MUX_IN_KPP_COL_1,
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MUX_IN_KPP_COL_2,
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MUX_IN_KPP_COL_3,
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MUX_IN_KPP_COL_4,
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MUX_IN_KPP_COL_5,
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MUX_IN_KPP_COL_6,
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MUX_IN_KPP_COL_7,
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MUX_IN_KPP_ROW_0,
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MUX_IN_KPP_ROW_1,
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MUX_IN_KPP_ROW_2,
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MUX_IN_KPP_ROW_3,
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MUX_IN_KPP_ROW_4,
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MUX_IN_KPP_ROW_5,
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MUX_IN_KPP_ROW_6,
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MUX_IN_KPP_ROW_7,
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MUX_IN_OWIRE_BATTERY_LINE,
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MUX_IN_SPDIF_HCKT_CLK2,
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MUX_IN_SPDIF_SPDIF_IN1,
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MUX_IN_UART3_UART_RTS_B,
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MUX_IN_UART3_UART_RXD_MUX,
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MUX_IN_USB_OTG_DATA_0,
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MUX_IN_USB_OTG_DATA_1,
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MUX_IN_USB_OTG_DATA_2,
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MUX_IN_USB_OTG_DATA_3,
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MUX_IN_USB_OTG_DATA_4,
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MUX_IN_USB_OTG_DATA_5,
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MUX_IN_USB_OTG_DATA_6,
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MUX_IN_USB_OTG_DATA_7,
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MUX_IN_USB_OTG_DIR,
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MUX_IN_USB_OTG_NXT,
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MUX_IN_USB_UH2_DATA_0,
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MUX_IN_USB_UH2_DATA_1,
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MUX_IN_USB_UH2_DATA_2,
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MUX_IN_USB_UH2_DATA_3,
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MUX_IN_USB_UH2_DATA_4,
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MUX_IN_USB_UH2_DATA_5,
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MUX_IN_USB_UH2_DATA_6,
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MUX_IN_USB_UH2_DATA_7,
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MUX_IN_USB_UH2_DIR,
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MUX_IN_USB_UH2_NXT,
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MUX_IN_USB_UH2_USB_OC,
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} iomux_input_select_t;
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/*
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* various IOMUX input functions
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*/
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typedef enum iomux_input_config {
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INPUT_CTL_PATH0 = 0x0,
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INPUT_CTL_PATH1,
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INPUT_CTL_PATH2,
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INPUT_CTL_PATH3,
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INPUT_CTL_PATH4,
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INPUT_CTL_PATH5,
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INPUT_CTL_PATH6,
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INPUT_CTL_PATH7,
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} iomux_input_cfg_t;
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/*
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* Request ownership for an IO pin. This function has to be the first one
|
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* being called before that pin is used. The caller has to check the
|
||||
* return value to make sure it returns 0.
|
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*
|
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* @param pin a name defined by iomux_pin_name_t
|
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* @param cfg an input function as defined in iomux_pin_cfg_t
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*
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* @return 0 if successful; Non-zero otherwise
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*/
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void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
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|
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/*
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* Release ownership for an IO pin
|
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*
|
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* @param pin a name defined by iomux_pin_name_t
|
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* @param cfg an input function as defined in iomux_pin_cfg_t
|
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*/
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void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
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|
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/*
|
||||
* This function enables/disables the general purpose function for a particular
|
||||
* signal.
|
||||
*
|
||||
* @param gp one signal as defined in iomux_gp_func_t
|
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* @param en 1 to enable; 0 to disable
|
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*/
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void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
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|
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/*
|
||||
* This function configures the pad value for a IOMUX pin.
|
||||
*
|
||||
* @param pin a pin number as defined in iomux_pin_name_t
|
||||
* @param config the ORed value of elements defined in
|
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* iomux_pad_config_t
|
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*/
|
||||
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
|
||||
|
||||
/*
|
||||
* This function configures input path.
|
||||
*
|
||||
* @param input index of input select register as defined in
|
||||
* iomux_input_select_t
|
||||
* @param config the binary value of elements defined in
|
||||
* iomux_input_cfg_t
|
||||
*/
|
||||
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
|
||||
#endif
|
||||
@@ -1,353 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
|
||||
#define __ASM_ARCH_MXC_MX35_PINS_H__
|
||||
|
||||
/*!
|
||||
* @file arch-mxc/mx35_pins.h
|
||||
*
|
||||
* @brief MX35 I/O Pin List
|
||||
*
|
||||
* @ingroup GPIO_MX35
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*!
|
||||
* @name IOMUX/PAD Bit field definitions
|
||||
*/
|
||||
|
||||
/*! @{ */
|
||||
|
||||
/*!
|
||||
* In order to identify pins more effectively, each mux-controlled pin's
|
||||
* enumerated value is constructed in the following way:
|
||||
*
|
||||
* -------------------------------------------------------------------
|
||||
* 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
|
||||
* -------------------------------------------------------------------
|
||||
* IO_P | IO_I | RSVD | PAD_I | MUX_I
|
||||
* -------------------------------------------------------------------
|
||||
*
|
||||
* Bit 0 to 7 contains MUX_I used to identify the register
|
||||
* offset (base is IOMUX_module_base ) defined in the Section
|
||||
* "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
|
||||
* definitions are used for the pad control register.the MX35_PIN_A0 is
|
||||
* defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
|
||||
* So the absolute address is: IOMUX_module_base + 0x28.
|
||||
* The pad control register offset is: 0x368.
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the
|
||||
* MUX control register offset
|
||||
*/
|
||||
#define MUX_I 0
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the
|
||||
* PAD control register offset
|
||||
*/
|
||||
#define PAD_I 10
|
||||
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the
|
||||
* reserved filed
|
||||
*/
|
||||
#define RSVD_I 21
|
||||
|
||||
#define MUX_IO_P 29
|
||||
#define MUX_IO_I 24
|
||||
#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
|
||||
GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
|
||||
((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
|
||||
#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
|
||||
|
||||
#define NON_GPIO_I 0x7
|
||||
#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
|
||||
#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
|
||||
#define NON_MUX_I PIN_TO_MUX_MASK
|
||||
|
||||
#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
|
||||
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
|
||||
((mi) << MUX_I) | ((pi) << PAD_I))
|
||||
|
||||
#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
|
||||
_MXC_BUILD_PIN(gp, gi, mi, pi)
|
||||
|
||||
#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
|
||||
_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
|
||||
|
||||
#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
|
||||
#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
|
||||
|
||||
/*! @} End IOMUX/PAD Bit field definitions */
|
||||
|
||||
/*!
|
||||
* This enumeration is constructed based on the Section
|
||||
* "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
|
||||
* value is constructed based on the rules described above.
|
||||
*/
|
||||
typedef enum iomux_pins {
|
||||
MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
|
||||
MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
|
||||
MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
|
||||
MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
|
||||
MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
|
||||
MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
|
||||
MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
|
||||
MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
|
||||
|
||||
MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
|
||||
MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
|
||||
MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
|
||||
MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
|
||||
MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
|
||||
MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
|
||||
MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
|
||||
MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
|
||||
MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
|
||||
MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
|
||||
MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
|
||||
MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
|
||||
MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
|
||||
MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
|
||||
MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
|
||||
MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
|
||||
MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
|
||||
MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
|
||||
MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
|
||||
MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
|
||||
MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
|
||||
MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
|
||||
MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
|
||||
MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
|
||||
MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
|
||||
MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
|
||||
MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
|
||||
MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
|
||||
MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
|
||||
|
||||
MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
|
||||
MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
|
||||
MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
|
||||
MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
|
||||
MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
|
||||
MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
|
||||
MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
|
||||
MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
|
||||
MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
|
||||
MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
|
||||
|
||||
MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
|
||||
MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
|
||||
MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
|
||||
|
||||
MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
|
||||
MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
|
||||
MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
|
||||
MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
|
||||
MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
|
||||
MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
|
||||
|
||||
MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
|
||||
MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
|
||||
MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
|
||||
MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
|
||||
MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
|
||||
MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
|
||||
MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
|
||||
MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
|
||||
MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
|
||||
MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
|
||||
MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
|
||||
MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
|
||||
MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
|
||||
MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
|
||||
MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
|
||||
MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
|
||||
|
||||
MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
|
||||
MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
|
||||
MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
|
||||
MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
|
||||
MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
|
||||
MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
|
||||
MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
|
||||
MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
|
||||
MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
|
||||
MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
|
||||
MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
|
||||
MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
|
||||
|
||||
MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
|
||||
MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
|
||||
MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
|
||||
MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
|
||||
|
||||
MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
|
||||
MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
|
||||
MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
|
||||
MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
|
||||
MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
|
||||
MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
|
||||
MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
|
||||
MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
|
||||
|
||||
MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
|
||||
MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
|
||||
MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
|
||||
MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
|
||||
MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
|
||||
MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
|
||||
MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
|
||||
MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
|
||||
MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
|
||||
MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
|
||||
MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
|
||||
MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
|
||||
|
||||
MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
|
||||
MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
|
||||
MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
|
||||
MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
|
||||
MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
|
||||
MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
|
||||
|
||||
MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
|
||||
MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
|
||||
MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
|
||||
MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
|
||||
MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
|
||||
MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
|
||||
MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
|
||||
MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
|
||||
|
||||
MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
|
||||
MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
|
||||
|
||||
MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
|
||||
MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
|
||||
MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
|
||||
MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
|
||||
MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
|
||||
MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
|
||||
MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
|
||||
MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
|
||||
MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
|
||||
MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
|
||||
MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
|
||||
MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
|
||||
MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
|
||||
MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
|
||||
MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
|
||||
MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
|
||||
MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
|
||||
MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
|
||||
MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
|
||||
MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
|
||||
MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
|
||||
MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
|
||||
MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
|
||||
MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
|
||||
|
||||
MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
|
||||
MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
|
||||
MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
|
||||
MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
|
||||
MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
|
||||
MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
|
||||
MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
|
||||
MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
|
||||
|
||||
MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
|
||||
MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
|
||||
MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
|
||||
MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
|
||||
MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
|
||||
MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
|
||||
MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
|
||||
MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
|
||||
MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
|
||||
MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
|
||||
MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
|
||||
MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
|
||||
|
||||
MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
|
||||
MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
|
||||
MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
|
||||
MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
|
||||
MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
|
||||
MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
|
||||
MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
|
||||
MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
|
||||
MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
|
||||
MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
|
||||
MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
|
||||
MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
|
||||
MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
|
||||
MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
|
||||
MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
|
||||
MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
|
||||
MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
|
||||
MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
|
||||
MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
|
||||
MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
|
||||
MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
|
||||
MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
|
||||
MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
|
||||
MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
|
||||
MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
|
||||
MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
|
||||
MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
|
||||
MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
|
||||
MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
|
||||
|
||||
MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
|
||||
MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
|
||||
MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
|
||||
|
||||
MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
|
||||
MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
|
||||
MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
|
||||
MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
|
||||
MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
|
||||
MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
|
||||
MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
|
||||
MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
|
||||
MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
|
||||
MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
|
||||
MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
|
||||
MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
|
||||
MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
|
||||
MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
|
||||
MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
|
||||
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
|
||||
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
|
||||
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
|
||||
} iomux_pin_name_t;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
Reference in New Issue
Block a user