dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-11-02 03:17:29 +01:00
Code Issues Packages Projects Releases Wiki Activity

arm: minor fixes for cache and mmu handling

Browse Source 
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
   than a range flush on the entire memory(flush_cache())

   Provide a default implementation for flush_dcache_all()
   for backward compatibility and to avoid build issues.

Signed-off-by: Aneesh V <aneesh@ti.com>
This commit is contained in:
Aneesh V
2011-06-16 23:30:50 +00:00
committed by Albert ARIBAUD
parent c2dd0d4554
commit e05f00792b
2 changed files with 18 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/lib/cache-cp15.c
View File

@@ -92,13 +92,18 @@ static inline void mmu_setup(void)
set_cr(reg | CR_M);
}
static int mmu_enabled(void)
{
return get_cr() & CR_M;
}
/* cache_bit must be either CR_I or CR_C */
static void cache_enable(uint32_t cache_bit)
{
uint32_t reg;
/* The data cache is not active unless the mmu is enabled too */
if (cache_bit == CR_C)
if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
reg = get_cr(); /* get control reg. */
cp_delay();
@@ -117,7 +122,7 @@ static void cache_disable(uint32_t cache_bit)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
flush_cache(0, ~0);
flush_dcache_all();
}
reg = get_cr();
cp_delay();