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p4080/serdes: Implement the XAUI workaround for SERDES9 erratum

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Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Emil Medve
2010-08-31 22:57:38 -05:00
committed by Kumar Gala
parent 3d28c5c8ed
commit df8af0b4a6
5 changed files with 116 additions and 0 deletions
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1
arch/powerpc/include/asm/config_mpc85xx.h
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@@ -304,6 +304,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)

3
arch/powerpc/include/asm/fsl_serdes.h
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@@ -55,6 +55,9 @@ void fsl_serdes_init(void);
#ifdef CONFIG_FSL_CORENET
int serdes_get_first_lane(enum srds_prtcl device);
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
void serdes_reset_rx(enum srds_prtcl device);
#endif
#endif
#endif /* __FSL_SERDES_H */

2
arch/powerpc/include/asm/immap_85xx.h
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@@ -2137,6 +2137,8 @@ typedef struct serdes_corenet {
#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
u32 res3;
u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
#define SRDS_TTLCR0_PM_DIS 0x00004000
u32 res4[7];
} lane[24];
u32 res6[384];