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treewide: Try to avoid the preprocessor with OF_REAL

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Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
2021-08-07 07:24:06 -06:00
parent 62470afed1
commit dcfc42b12f
21 changed files with 167 additions and 156 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/x86/cpu/intel_common/p2sb.c
View File

@@ -159,7 +159,7 @@ static int p2sb_remove(struct udevice *dev)
static int p2sb_child_post_bind(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
@@ -168,7 +168,7 @@ static int p2sb_child_post_bind(struct udevice *dev)
if (ret)
return ret;
pplat->pid = pid;
#endif
}
return 0;
}

4
doc/develop/driver-model/of-plat.rst
View File

@@ -215,14 +215,14 @@ For example:
static int mmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
/* Decode the devicetree data */
struct mmc_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
#endif
}
return 0;
}

4
drivers/clk/clk_fixed_factor.c
View File

@@ -40,7 +40,7 @@ const struct clk_ops clk_fixed_factor_ops = {
static int clk_fixed_factor_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
int err;
struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
@@ -50,7 +50,7 @@ static int clk_fixed_factor_of_to_plat(struct udevice *dev)
ff->div = dev_read_u32_default(dev, "clock-div", 1);
ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
#endif
}
return 0;
}

7
drivers/clk/clk_fixed_rate.c
View File

@@ -32,9 +32,10 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
struct clk_fixed_rate *plat)
{
struct clk *clk = &plat->clk;
#if CONFIG_IS_ENABLED(OF_REAL)
plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0);
#endif
if (CONFIG_IS_ENABLED(OF_REAL))
plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency",
0);
/* Make fixed rate clock accessible from higher level struct clk */
/* FIXME: This is not allowed */
dev_set_uclass_priv(dev, clk);

4
drivers/clk/rockchip/clk_rk3188.c
View File

@@ -540,11 +540,11 @@ static struct clk_ops rk3188_clk_ops = {
static int rk3188_clk_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3188_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
#endif
}
return 0;
}

4
drivers/clk/rockchip/clk_rk3288.c
View File

@@ -957,11 +957,11 @@ static struct clk_ops rk3288_clk_ops = {
static int rk3288_clk_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3288_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
#endif
}
return 0;
}

4
drivers/clk/rockchip/clk_rk3368.c
View File

@@ -596,11 +596,11 @@ static int rk3368_clk_probe(struct udevice *dev)
static int rk3368_clk_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3368_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
#endif
}
return 0;
}

10
drivers/clk/rockchip/clk_rk3399.c
View File

@@ -1402,11 +1402,12 @@ static int rk3399_clk_probe(struct udevice *dev)
static int rk3399_clk_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3399_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
#endif
}
return 0;
}
@@ -1614,11 +1615,12 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
priv->pmucru = dev_read_addr_ptr(dev);
#endif
}
return 0;
}

4
drivers/misc/p2sb-uclass.c
View File

@@ -183,7 +183,7 @@ int p2sb_set_port_id(struct udevice *dev, int portid)
static int p2sb_child_post_bind(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
@@ -192,7 +192,7 @@ static int p2sb_child_post_bind(struct udevice *dev)
if (ret)
return ret;
pplat->pid = pid;
#endif
}
return 0;
}

11
drivers/mmc/fsl_esdhc_imx.c
View File

@@ -1411,7 +1411,6 @@ __weak void init_clk_usdhc(u32 index)
static int fsl_esdhc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
@@ -1419,10 +1418,12 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
#endif
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
fdt_addr_t addr;
unsigned int val;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -1494,7 +1495,7 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
priv->vs18_enable = 1;
}
#endif
#endif
return 0;
}
@@ -1598,11 +1599,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
return ret;
}
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
#endif
}
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;

5
drivers/mmc/ftsdc010_mci.c
View File

@@ -390,10 +390,10 @@ static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswid
static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
if (CONFIG_IS_ENABLED(OF_REAL)) {
chip->name = dev->name;
chip->ioaddr = dev_read_addr_ptr(dev);
chip->buswidth = dev_read_u32_default(dev, "bus-width", 4);
@@ -409,9 +409,10 @@ static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
}
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
return 0;
}

6
drivers/mmc/rockchip_dw_mmc.c
View File

@@ -52,10 +52,12 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
@@ -95,7 +97,7 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
return 0;
}

4
drivers/ram/rockchip/dmc-rk3368.c
View File

@@ -883,13 +883,13 @@ static int rk3368_dmc_of_to_plat(struct udevice *dev)
{
int ret = 0;
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3368_sdram_params *plat = dev_get_plat(dev);
ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
if (ret)
return ret;
#endif
}
return ret;
}

5
drivers/ram/rockchip/sdram_rk3188.c
View File

@@ -816,10 +816,12 @@ static int setup_sdram(struct udevice *dev)
static int rk3188_dmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3188_sdram_params *params = dev_get_plat(dev);
int ret;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
/* rk3188 supports only one-channel */
params->num_channels = 1;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
@@ -846,7 +848,6 @@ static int rk3188_dmc_of_to_plat(struct udevice *dev)
ret = regmap_init_mem(dev_ofnode(dev), &params->map);
if (ret)
return ret;
#endif
return 0;
}

5
drivers/ram/rockchip/sdram_rk322x.c
View File

@@ -716,12 +716,14 @@ out:
static int rk322x_dmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct rk322x_sdram_params *params = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
params->num_channels = 1;
ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
@@ -748,7 +750,6 @@ static int rk322x_dmc_of_to_plat(struct udevice *dev)
ret = regmap_init_mem(dev_ofnode(dev), &params->map);
if (ret)
return ret;
#endif
return 0;
}

5
drivers/ram/rockchip/sdram_rk3288.c
View File

@@ -973,10 +973,12 @@ static int setup_sdram(struct udevice *dev)
static int rk3288_dmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3288_sdram_params *params = dev_get_plat(dev);
int ret;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
/* Rk3288 supports dual-channel, set default channel num to 2 */
params->num_channels = 2;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
@@ -1008,7 +1010,6 @@ static int rk3288_dmc_of_to_plat(struct udevice *dev)
ret = regmap_init_mem(dev_ofnode(dev), &params->map);
if (ret)
return ret;
#endif
return 0;
}

5
drivers/ram/rockchip/sdram_rk3399.c
View File

@@ -3013,10 +3013,12 @@ static int sdram_init(struct dram_info *dram,
static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
if (!CONFIG_IS_ENABLED(OF_REAL))
return 0;
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
(u32 *)&plat->sdram_params,
sizeof(plat->sdram_params) / sizeof(u32));
@@ -3029,7 +3031,6 @@ static int rk3399_dmc_of_to_plat(struct udevice *dev)
if (ret)
printf("%s: regmap failed %d\n", __func__, ret);
#endif
return 0;
}

8
drivers/spi/rk_spi.c
View File

@@ -193,11 +193,11 @@ static int conv_of_plat(struct udevice *dev)
static int rockchip_spi_of_to_plat(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
if (CONFIG_IS_ENABLED(OF_REAL)) {
plat->base = dev_read_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
@@ -207,8 +207,8 @@ static int rockchip_spi_of_to_plat(struct udevice *bus)
return ret;
}
plat->frequency =
dev_read_u32_default(bus, "spi-max-frequency", 50000000);
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
50000000);
plat->deactivate_delay_us =
dev_read_u32_default(bus, "spi-deactivate-delay", 0);
plat->activate_delay_us =
@@ -217,7 +217,7 @@ static int rockchip_spi_of_to_plat(struct udevice *bus)
debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
__func__, (uint)plat->base, plat->frequency,
plat->deactivate_delay_us);
#endif
}
return 0;
}

4
drivers/spi/spi-uclass.c
View File

@@ -176,11 +176,11 @@ static int spi_child_post_bind(struct udevice *dev)
static int spi_post_probe(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
#endif
}
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
static int reloc_done;

8
drivers/timer/rockchip_timer.c
View File

@@ -55,8 +55,7 @@ ulong timer_get_boot_us(void)
/* The timer is available */
rate = timer_get_rate(gd->timer);
timer_get_count(gd->timer, &ticks);
#if CONFIG_IS_ENABLED(OF_REAL)
} else if (ret == -EAGAIN) {
} else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
/* We have been called so early that the DM is not ready,... */
ofnode node = offset_to_ofnode(-1);
struct rk_timer *timer = NULL;
@@ -79,7 +78,6 @@ ulong timer_get_boot_us(void)
debug("%s: could not read clock-frequency\n", __func__);
return 0;
}
#endif
} else {
return 0;
}
@@ -100,13 +98,13 @@ static u64 rockchip_timer_get_count(struct udevice *dev)
static int rockchip_clk_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rockchip_timer_priv *priv = dev_get_priv(dev);
priv->timer = dev_read_addr_ptr(dev);
if (!priv->timer)
return -ENOENT;
#endif
}
return 0;
}

12
drivers/timer/timer-uclass.c
View File

@@ -50,13 +50,15 @@ unsigned long notrace timer_get_rate(struct udevice *dev)
static int timer_pre_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk timer_clk;
int err;
ulong ret;
/* It is possible that a timer device has a null ofnode */
/*
* It is possible that a timer device has a null ofnode
*/
if (!dev_has_ofnode(dev))
return 0;
@@ -70,7 +72,7 @@ static int timer_pre_probe(struct udevice *dev)
uc_priv->clock_rate =
dev_read_u32_default(dev, "clock-frequency", 0);
}
#endif
}
return 0;
}
@@ -136,7 +138,7 @@ int notrace dm_timer_init(void)
if (gd->dm_root == NULL)
return -EAGAIN;
#if CONFIG_IS_ENABLED(OF_REAL)
if (CONFIG_IS_ENABLED(OF_REAL)) {
/* Check for a chosen timer to be used for tick */
node = ofnode_get_chosen_node("tick-timer");
@@ -152,7 +154,7 @@ int notrace dm_timer_init(void)
return ret;
}
}
#endif
}
if (!dev) {
/* Fall back to the first available timer */