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stm32f7: enable instruction & data cache

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It also enables commands for cache enable/disable/status.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
This commit is contained in:
Vikas Manocha
2017-03-27 13:02:45 -07:00
committed by Tom Rini
parent bf4d0495d2
commit dc11d83a2e
2 changed files with 3 additions and 3 deletions
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2
arch/arm/mach-stm32/stm32f7/soc.c
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@@ -58,6 +58,8 @@ int arch_cpu_init(void)
(V7M_MPU_RASR_XN_ENABLE
| V7M_MPU_RASR_AP_RW_RW
| 0x01 << V7M_MPU_RASR_TEX_SHIFT
| 0x01 << V7M_MPU_RASR_B_SHIFT
| 0x01 << V7M_MPU_RASR_C_SHIFT
| V7M_MPU_RASR_SIZE_8MB
| V7M_MPU_RASR_EN)
, &V7M_MPU->rasr