Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-07 03:05:19 +02:00 · 2018-12-10 17:12:52 -05:00
parent 2918f58faa 4909b89ec7
commit d94604d558
112 changed files with 4104 additions and 543 deletions
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright 2016-2018 NXP
 * Copyright 2015, Freescale Semiconductor
 */

@@ -176,6 +177,61 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */

+/* LX2160A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A)
+#define TZPC_BASE				0x02200000
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define SRDS_MAX_LANES  8
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
+#endif
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		4
+
+#define CONFIG_SYS_PAGE_SIZE			0x10000
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE				0x06000000
+#define GICR_BASE				0x06200000
+
+/* SMMU Definitions */
+#define SMMU_BASE				0x05000000 /* GR0 Base */
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,50 +1,30 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
 * Copyright 2014-2015, Freescale Semiconductor
 */

 #ifndef _FSL_LAYERSCAPE_CPU_H
 #define _FSL_LAYERSCAPE_CPU_H

-static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
-	CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
-	CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
-	CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
-	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
-	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
-	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
-	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
-	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
-	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
-	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
-	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
-	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
-	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
-	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
-	CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
-	CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
-	CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
-	CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
-};
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
 #ifdef CONFIG_FSL_LSCH3
 #define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
 #define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
 #define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
 #define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
+#ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
 #define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
 #define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
+#endif
 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
 #define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
 #define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
+#ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
 #define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
+#endif
 #define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
 #define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
 #define CONFIG_SYS_FSL_MC_BASE		0x80c000000
@@ -64,8 +44,15 @@ static struct cpu_type cpu_type_list[] = {
 #define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
 #define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
 #define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
+#ifdef CONFIG_NXP_LSCH3_2
+#define CONFIG_SYS_FSL_DRAM_BASE2	0x2080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2	0x1F80000000
+#define CONFIG_SYS_FSL_DRAM_BASE3	0x6000000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3	0x2000000000
+#else
 #define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
+#endif
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_BOOTROM_BASE	0x0
 #define CONFIG_SYS_FSL_BOOTROM_SIZE	0x1000000
@@ -90,282 +77,6 @@ static struct cpu_type cpu_type_list[] = {
 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
 #endif

-#define EARLY_PGTABLE_SIZE 0x5000
-static struct mm_region early_map[] = {
-#ifdef CONFIG_FSL_LSCH3
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  SYS_FSL_OCRAM_SPACE_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-	},
-	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-	  CONFIG_SYS_FSL_QSPI_SIZE1,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
-#ifdef CONFIG_FSL_IFC
-	/* For IFC Region #1, only the first 4MB is cache-enabled */
-	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-	},
-	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-	},
-	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-	},
-#endif
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else	/* Start with nGnRnE and PXN and UXN to prevent speculative access */
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-#ifdef CONFIG_FSL_IFC
-	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
-	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-	},
-#endif
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-#elif defined(CONFIG_FSL_LSCH2)
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  SYS_FSL_OCRAM_SPACE_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-	},
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-	},
-#ifdef CONFIG_FSL_IFC
-	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-	},
-#endif
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else	/* Start with nGnRnE and PXN and UXN to prevent speculative access */
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-#endif
-	{},	/* list terminator */
-};
-
-static struct mm_region final_map[] = {
-#ifdef CONFIG_FSL_LSCH3
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  SYS_FSL_OCRAM_SPACE_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-	},
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-	  CONFIG_SYS_FSL_QSPI_SIZE1,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-	  CONFIG_SYS_FSL_QSPI_SIZE2,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-#ifdef CONFIG_FSL_IFC
-	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FSL_IFC_SIZE2,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-#endif
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-	  CONFIG_SYS_FSL_MC_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-	  CONFIG_SYS_FSL_NI_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	/* For QBMAN portal, only the first 64MB is cache-enabled */
-	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
-	},
-	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-#ifdef CONFIG_ARCH_LS2080A
-	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CONFIG_SYS_PCIE4_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-#endif
-	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-	  CONFIG_SYS_FSL_WRIOP1_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-	  CONFIG_SYS_FSL_AIOP1_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-	  CONFIG_SYS_FSL_PEBUF_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-#elif defined(CONFIG_FSL_LSCH2)
-	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
-	  CONFIG_SYS_FSL_BOOTROM_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  SYS_FSL_OCRAM_SPACE_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-	},
-	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-#ifdef CONFIG_FSL_IFC
-	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-	},
-#endif
-	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
-	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-	  CONFIG_SYS_FSL_DRAM_SIZE3,
-	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	},
-#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-	{},	/* space holder for secure mem */
-#endif
-	{},
-};
-#endif	/* !CONFIG_SYS_DCACHE_OFF */
-
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 cpu_mask(void);

--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright 2018 NXP
 * Copyright 2015 Freescale Semiconductor, Inc.
 */

@@ -19,8 +20,12 @@ enum srds_prtcl {
 	PCIE2,
 	PCIE3,
 	PCIE4,
+	PCIE5,
+	PCIE6,
 	SATA1,
 	SATA2,
+	SATA3,
+	SATA4,
 	XAUI1,
 	XAUI2,
 	XFI1,
@@ -31,6 +36,12 @@ enum srds_prtcl {
 	XFI6,
 	XFI7,
 	XFI8,
+	XFI9,
+	XFI10,
+	XFI11,
+	XFI12,
+	XFI13,
+	XFI14,
 	SGMII1,
 	SGMII2,
 	SGMII3,
@@ -47,16 +58,35 @@ enum srds_prtcl {
 	SGMII14,
 	SGMII15,
 	SGMII16,
+	SGMII17,
+	SGMII18,
 	QSGMII_A,
 	QSGMII_B,
 	QSGMII_C,
 	QSGMII_D,
+	_25GE1,
+	_25GE2,
+	_25GE3,
+	_25GE4,
+	_25GE5,
+	_25GE6,
+	_25GE7,
+	_25GE8,
+	_25GE9,
+	_25GE10,
+	_40GE1,
+	_40GE2,
+	_50GE1,
+	_50GE2,
+	_100GE1,
+	_100GE2,
 	SERDES_PRCTL_COUNT
 };

 enum srds {
 	FSL_SRDS_1  = 0,
 	FSL_SRDS_2  = 1,
+	NXP_SRDS_3  = 2,
 };
 #elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -677,6 +677,26 @@ struct ccsr_gpio {
 #define SCR0_CLIENTPD_MASK		0x00000001
 #define SCR0_USFCFG_MASK		0x00000400

+#ifdef CONFIG_TFABOOT
+#define RCW_SRC_MASK			(0xFF800000)
+#define RCW_SRC_BIT			23
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK		(0x100)
+#define RCW_SRC_NAND_VAL		(0x100)
+#define NAND_RESERVED_MASK		(0xFC)
+#define NAND_RESERVED_1			(0x0)
+#define NAND_RESERVED_2			(0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK		(0x1F0)
+#define NOR_8B_VAL			(0x10)
+#define NOR_16B_VAL			(0x20)
+#define SD_VAL				(0x40)
+#define QSPI_VAL1			(0x44)
+#define QSPI_VAL2			(0x45)
+#endif
+
 uint get_svr(void);

 #endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
 /*
 * LayerScape Internal Memory Map
 *
- * Copyright (C) 2017 NXP Semiconductors
+ * Copyright 2017-2018 NXP
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

@@ -15,13 +15,19 @@
 #define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
 #define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
+#else
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
+#endif
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
+#ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
+#endif
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR	0x023d0000
@@ -45,6 +51,12 @@
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+#ifdef CONFIG_NXP_LSCH3_2
+#define I2C5_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01040000)
+#define I2C6_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01050000)
+#define I2C7_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01060000)
+#define I2C8_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01070000)
+#endif
 #define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01330000)
 #define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
 #define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
@@ -82,6 +94,55 @@
 #define CONFIG_SYS_FSL_JR0_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)

+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_NXP_LSCH3_2
+/* RCW_SRC field in Power-On Reset Control Register 1 */
+#define RCW_SRC_MASK			0x07800000
+#define RCW_SRC_BIT			23
+
+/* CFG_RCW_SRC[3:0] */
+#define RCW_SRC_TYPE_MASK		0x8
+#define RCW_SRC_ADDR_OFFSET_8MB		0x800000
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL		0x0	/* 0x00 - 0x07 */
+
+#define RCW_SRC_SDHC1_VAL		0x8	/* 0x8 */
+#define RCW_SRC_SDHC2_VAL		0x9	/* 0x9 */
+#define RCW_SRC_I2C1_VAL		0xa	/* 0xa */
+#define RCW_SRC_RESERVED_UART_VAL	0xb	/* 0xb */
+#define RCW_SRC_FLEXSPI_NAND2K_VAL	0xc	/* 0xc */
+#define RCW_SRC_FLEXSPI_NAND4K_VAL	0xd	/* 0xd */
+#define RCW_SRC_RESERVED_1_VAL		0xe	/* 0xe */
+#define RCW_SRC_FLEXSPI_NOR_24B		0xf	/* 0xf */
+#else
+#define RCW_SRC_MASK			(0xFF800000)
+#define RCW_SRC_BIT			23
+/* CFG_RCW_SRC[6:0] */
+#define RCW_SRC_TYPE_MASK               (0x70)
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL           (0x10)     /* 0x10 - 0x1f */
+/* Hardcoded will also have CFG_RCW_SRC[7] as 1.   0x90 - 0x9f */
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_VAL                 (0x20)
+#define NOR_TYPE_MASK                   (0x10)
+#define NOR_16B_VAL                     (0x0)       /* 0x20 - 0x2f */
+#define NOR_32B_VAL                     (0x10)       /* 0x30 - 0x3f */
+
+/* RCW SRC Serial Flash
+ * 1. SERIAL NOR (QSPI)
+ * 2. OTHERS (SD/MMC, SPI, I2C1
+ */
+#define RCW_SRC_SERIAL_MASK             (0x7F)
+#define RCW_SRC_QSPI_VAL                (0x62)     /* 0x62 */
+#define RCW_SRC_SD_CARD_VAL             (0x40)     /* 0x40 */
+#define RCW_SRC_EMMC_VAL                (0x41)     /* 0x41 */
+#define RCW_SRC_I2C1_VAL                (0x49)     /* 0x49 */
+#endif
+#endif
+
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)

@@ -267,6 +328,28 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR	29
 #define FSL_CHASSIS3_SRDS2_REGSR	29
+#elif defined(CONFIG_ARCH_LX2160A)
+#define FSL_CHASSIS3_EC1_REGSR  27
+#define FSL_CHASSIS3_EC2_REGSR  27
+#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK	0x00000003
+#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT	0
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK	0x00000007
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT	2
+#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x001F0000
+#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0x03E00000
+#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  21
+#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK   0x7C000000
+#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT  26
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS3_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	29
+#define FSL_CHASSIS3_SRDS3_REGSR	29
 #elif defined(CONFIG_ARCH_LS1088A)
 #define FSL_CHASSIS3_EC1_REGSR  26
 #define FSL_CHASSIS3_EC2_REGSR  26
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -53,6 +53,28 @@ struct cpu_type {

 #define CPU_TYPE_ENTRY(n, v, nc) \
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#ifdef CONFIG_TFABOOT
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+#define SIP_SVC_RCW	0xC200FF18
+
+phys_size_t tfa_get_dram_size(void);
+
+enum boot_src {
+	BOOT_SOURCE_RESERVED = 0,
+	BOOT_SOURCE_IFC_NOR,
+	BOOT_SOURCE_IFC_NAND,
+	BOOT_SOURCE_QSPI_NOR,
+	BOOT_SOURCE_QSPI_NAND,
+	BOOT_SOURCE_XSPI_NOR,
+	BOOT_SOURCE_XSPI_NAND,
+	BOOT_SOURCE_SD_MMC,
+	BOOT_SOURCE_SD_MMC2,
+	BOOT_SOURCE_I2C1_EXTENDED,
+};
+
+enum boot_src get_boot_src(void);
+#endif
 #endif
 #define SVR_WO_E		0xFFFFFE
 #define SVR_LS1012A		0x870400
@@ -74,12 +96,18 @@ struct cpu_type {
 #define SVR_LS2044A		0x870930
 #define SVR_LS2081A		0x870918
 #define SVR_LS2041A		0x870914
+#define SVR_LX2160A		0x873601
+#define SVR_LX2120A		0x873621
+#define SVR_LX2080A		0x873603

 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
 #define SVR_REV(svr)		(((svr) >> 0) & 0xff)
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
+#ifdef CONFIG_ARCH_LX2160A
+#define IS_C_PROCESSOR(svr)	(!((svr >> 12) & 0x1))
+#endif
 #define IS_SVR_REV(svr, maj, min) \
 		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
 #define SVR_DEV(svr)		((svr) >> 8)
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright 2015-2018 NXP
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 */
@@ -69,11 +70,11 @@
 #define FSL_SDMMC_STREAM_ID		3
 #define FSL_SATA1_STREAM_ID		4

-#if defined(CONFIG_ARCH_LS2080A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
 #define FSL_SATA2_STREAM_ID		5
 #endif

-#if defined(CONFIG_ARCH_LS2080A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
 #define FSL_DMA_STREAM_ID		6
 #elif defined(CONFIG_ARCH_LS1088A)
 #define FSL_DMA_STREAM_ID		5
@@ -82,6 +83,10 @@
 /* PCI - programmed in PEXn_LUT */
 #define FSL_PEX_STREAM_ID_START		7

+#ifdef CONFIG_ARCH_LX2160A
+#define FSL_PEX_STREAM_ID_NUM		(0x100)
+#endif
+
 #if defined(CONFIG_ARCH_LS2080A)
 #define FSL_PEX_STREAM_ID_END		22
 #elif defined(CONFIG_ARCH_LS1088A)