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board: AM335x-ICEv2: Add DDR data

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AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125),
capable of running at 400MHz. Adding this specific DDR configuration
details running at 400MHz.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
2016-05-16 11:47:24 +05:30
committed by Tom Rini
parent 866b178bd1
commit d8ff4fdb10
2 changed files with 55 additions and 1 deletions
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15
arch/arm/include/asm/arch-am33xx/ddr_defs.h
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@@ -54,6 +54,21 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 at 400MHz*/
#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
#define MT41J128MJT125_RATIO_400MHz 0x80
#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
#define MT41J128MJT125_RD_DQS_400MHz 0x3A
#define MT41J128MJT125_WR_DQS_400MHz 0x3B
#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
/* Micron MT41K128M16JT-187E */
#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB