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Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
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@@ -703,14 +703,14 @@ struct dram_timing_info {
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extern struct dram_timing_info dram_timing;
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void ddr_load_train_firmware(enum fw_type type);
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void ddr_init(struct dram_timing_info *timing_info);
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void ddr_cfg_phy(struct dram_timing_info *timing_info);
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int ddr_init(struct dram_timing_info *timing_info);
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int ddr_cfg_phy(struct dram_timing_info *timing_info);
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void load_lpddr4_phy_pie(void);
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void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
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void dram_config_save(struct dram_timing_info *info, unsigned long base);
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/* utils function for ddr phy training */
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void wait_ddrphy_training_complete(void);
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int wait_ddrphy_training_complete(void);
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void ddrphy_init_set_dfi_clk(unsigned int drate);
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void ddrphy_init_read_msg_block(enum fw_type type);
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@@ -24,8 +24,10 @@ struct mxs_clkctrl_regs {
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mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
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mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
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mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
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mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */
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mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */
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uint32_t hw_clkctrl_ssp0; /* 0x70 */
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uint32_t reserved_ssp0[3]; /* 0x74-0x7c */
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uint32_t hw_clkctrl_gpmi; /* 0x80 */
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uint32_t reserved_gpmi[3]; /* 0x84-0x8c */
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mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
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mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */
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@@ -27,11 +27,16 @@ struct mxs_clkctrl_regs {
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mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
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mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
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mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
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mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
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mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
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mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
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mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
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mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
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uint32_t hw_clkctrl_ssp0; /* 0x90 */
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uint32_t reserved_ssp0[3]; /* 0x94-0x9c */
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uint32_t hw_clkctrl_ssp1; /* 0xa0 */
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uint32_t reserved_ssp1[3]; /* 0xa4-0xac */
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uint32_t hw_clkctrl_ssp2; /* 0xb0 */
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uint32_t reserved_ssp2[3]; /* 0xb4-0xbc */
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uint32_t hw_clkctrl_ssp3; /* 0xc0 */
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uint32_t reserved_ssp3[3]; /* 0xc4-0xcc */
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uint32_t hw_clkctrl_gpmi; /* 0xd0 */
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uint32_t reserved_gpmi[3]; /* 0xd4-0xdc */
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mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
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mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
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mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
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@@ -106,6 +106,13 @@ void gpr_init(void);
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#endif /* CONFIG_MX6 */
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/* address translation table */
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struct rproc_att {
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u32 da; /* device address (From Cortex M4 view) */
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u32 sa; /* system bus address */
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u32 size; /* size of reg range */
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};
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#ifdef CONFIG_IMX8M
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struct rom_api {
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u16 ver;
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