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mirror of https://xff.cz/git/u-boot/ synced 2025-10-09 20:16:27 +02:00
New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
This commit is contained in:
Tom Rini
2020-01-07 08:45:43 -05:00
207 changed files with 13950 additions and 3277 deletions

View File

@@ -703,14 +703,14 @@ struct dram_timing_info {
extern struct dram_timing_info dram_timing;
void ddr_load_train_firmware(enum fw_type type);
void ddr_init(struct dram_timing_info *timing_info);
void ddr_cfg_phy(struct dram_timing_info *timing_info);
int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void dram_config_save(struct dram_timing_info *info, unsigned long base);
/* utils function for ddr phy training */
void wait_ddrphy_training_complete(void);
int wait_ddrphy_training_complete(void);
void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);

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@@ -24,8 +24,10 @@ struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */
mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */
uint32_t hw_clkctrl_ssp0; /* 0x70 */
uint32_t reserved_ssp0[3]; /* 0x74-0x7c */
uint32_t hw_clkctrl_gpmi; /* 0x80 */
uint32_t reserved_gpmi[3]; /* 0x84-0x8c */
mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */

View File

@@ -27,11 +27,16 @@ struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
uint32_t hw_clkctrl_ssp0; /* 0x90 */
uint32_t reserved_ssp0[3]; /* 0x94-0x9c */
uint32_t hw_clkctrl_ssp1; /* 0xa0 */
uint32_t reserved_ssp1[3]; /* 0xa4-0xac */
uint32_t hw_clkctrl_ssp2; /* 0xb0 */
uint32_t reserved_ssp2[3]; /* 0xb4-0xbc */
uint32_t hw_clkctrl_ssp3; /* 0xc0 */
uint32_t reserved_ssp3[3]; /* 0xc4-0xcc */
uint32_t hw_clkctrl_gpmi; /* 0xd0 */
uint32_t reserved_gpmi[3]; /* 0xd4-0xdc */
mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */

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@@ -106,6 +106,13 @@ void gpr_init(void);
#endif /* CONFIG_MX6 */
/* address translation table */
struct rproc_att {
u32 da; /* device address (From Cortex M4 view) */
u32 sa; /* system bus address */
u32 size; /* size of reg range */
};
#ifdef CONFIG_IMX8M
struct rom_api {
u16 ver;