dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-09-29 22:41:17 +02:00
Code Issues Packages Projects Releases Wiki Activity

doc: Chromebook Coral: fix build warnings

Browse Source 
Use valid restructured text to avoid warnings like

WARNING: Title underline too short.
WARNING: Block quote ends without a blank line; unexpected unindent.

when building with `make htmldocs`.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Heinrich Schuchardt
2020-01-09 20:33:32 +01:00
committed by Bin Meng
parent 2fa863e9aa
commit d88030a83b
1 changed files with 41 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
doc/board/google/chromebook_coral.rst
View File

@@ -112,7 +112,7 @@ U-Boot then shuts down CAR and jumps to its relocated version.
Boot flow - U-Boot post-relocation
---------------------------------
----------------------------------
U-Boot starts up normally, running near the top of RAM. After driver model is
running, arch_fsp_init_r() is called which loads and runs the FSP-S binary.
@@ -142,9 +142,9 @@ Performance
-----------
Bootstage is used through all phases of U-Boot to keep accurate timimgs for
boot. Use 'bootstage report' in U-Boot to see the report, e.g.:
boot. Use 'bootstage report' in U-Boot to see the report, e.g.::
Timer summary in microseconds (16 records):
Timer summary in microseconds (16 records):
Mark Elapsed Stage
0 0 reset
155,325 155,325 TPL
@@ -156,7 +156,7 @@ Timer summary in microseconds (16 records):
1,166,233 323,469 main_loop
1,166,283 50 id=175
Accumulated time:
Accumulated time:
62 fast_spi
202 dm_r
7,779 dm_spl
@@ -165,26 +165,28 @@ Accumulated time:
239,847 fsp-s
292,143 mmap_spi
CPU performance is about 3500 DMIPS:
CPU performance is about 3500 DMIPS::
=> dhry
1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS
=> dhry
1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS
Partial memory map
------------------
ffffffff Top of ROM (and last byte of 32-bit address space)
ffff8000 TPL loaded here (from IFWI)
ff000000 Bottom of ROM
fefc000 Top of CAR region
fef96000 Stack for FSP-M
fef40000 59000 FSP-M
fef11000 SPL loaded here
fef10000 CONFIG_BLOBLIST_ADDR
fef10000 Stack top in TPL, SPL and U-Boot before relocation
fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR
fef00000 Base of CAR region
::
ffffffff Top of ROM (and last byte of 32-bit address space)
ffff8000 TPL loaded here (from IFWI)
ff000000 Bottom of ROM
fefc000 Top of CAR region
fef96000 Stack for FSP-M
fef40000 59000 FSP-M
fef11000 SPL loaded here
fef10000 CONFIG_BLOBLIST_ADDR
fef10000 Stack top in TPL, SPL and U-Boot before relocation
fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR
fef00000 Base of CAR region
f0000 CONFIG_ROM_TABLE_ADDR
120000 BSS (defined in u-boot-spl.lds)