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ARM: OMAP5: Add registers and defines for USBOTG SS

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Add the prcm registers and the bit definitions to enable the
USB SS port of the OMAP5 device.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
This commit is contained in:
Dan Murphy
2013-08-26 08:54:50 -05:00
committed by Marek Vasut
parent 1bd435bc70
commit d861a333da
4 changed files with 20 additions and 2 deletions
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4
arch/arm/include/asm/omap_common.h
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@@ -143,6 +143,7 @@ struct prcm_regs {
u32 cm_div_m2_dpll_unipro;
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy_core_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
@@ -226,6 +227,8 @@ struct prcm_regs {
u32 cm_l3init_p1500_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
u32 cm_l3init_usb_otg_ss_clkctrl;
u32 prm_irqstatus_mpu_2;
@@ -348,6 +351,7 @@ struct omap_sys_ctrl_regs {
u32 control_core_mac_id_1_lo;
u32 control_core_mac_id_1_hi;
u32 control_std_fuse_opp_vdd_mpu_2;
u32 control_phy_power_usb;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
u32 control_core_mmr_lock3;