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arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined

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Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Christian Riesch
2012-02-02 00:44:40 +00:00
committed by Albert ARIBAUD
parent b67d8816fd
commit d735a99d3b
1 changed files with 4 additions and 1 deletions
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5
arch/arm/cpu/arm926ejs/start.S
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@@ -369,7 +369,8 @@ flush_dcache:
mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
/* /*
* disable MMU and D cache, and enable I cache * disable MMU and D cache
* enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
*/ */
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
@@ -380,7 +381,9 @@ flush_dcache:
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif #endif
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
#ifndef CONFIG_SYS_ICACHE_OFF
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
/* /*