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armv8:fsl-layerscape: Add support for Chassis 3.2

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NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Priyanka Jain
2018-10-29 09:11:29 +00:00
committed by York Sun
parent db1e3df7ce
commit d6fdec211f
5 changed files with 68 additions and 5 deletions
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12
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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@@ -2,7 +2,7 @@
/*
* LayerScape Internal Memory Map
*
* Copyright (C) 2017 NXP Semiconductors
* Copyright 2017-2018 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -21,7 +21,9 @@
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
@@ -45,6 +47,12 @@
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
#ifdef CONFIG_NXP_LSCH3_2
#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
#endif
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
@@ -83,7 +91,7 @@
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#ifdef CONFIG_TFABOOT
#ifdef CONFIG_FSL_LSCH3_2
#ifdef CONFIG_NXP_LSCH3_2
/* RCW_SRC field in Power-On Reset Control Register 1 */
#define RCW_SRC_MASK 0x07800000
#define RCW_SRC_BIT 23