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ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

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AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
2013-12-10 15:02:22 +05:30
committed by Tom Rini
parent 965de8b91b
commit d3daba10f1
8 changed files with 256 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
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@@ -28,6 +28,9 @@
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
#define CM_DLL_READYST 0x4
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;

5
arch/arm/include/asm/arch-am33xx/cpu.h
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@@ -401,6 +401,11 @@ struct cm_perpll {
unsigned int cpgmac0clkctrl; /* offset 0xB20 */
};
struct cm_device_inst {
unsigned int cm_clkout1_ctrl;
unsigned int cm_dll_ctrl;
};
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */

33
arch/arm/include/asm/arch-am33xx/ddr_defs.h
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@@ -18,7 +18,11 @@
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#ifdef CONFIG_AM43XX
#define DDR_CKE_CTRL_NORMAL 0x3
#else
#define DDR_CKE_CTRL_NORMAL 0x1
#endif
#define PHY_EN_DYN_PWRDN (0x1 << 20)
/* Micron MT47H128M16RT-25E */
@@ -124,6 +128,14 @@
#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
/**
* Configure DMM
*/
@@ -133,6 +145,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs);
* Configure SDRAM
*/
void config_sdram(const struct emif_regs *regs, int nr);
void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
/**
* Set SDRAM timings
@@ -278,12 +291,27 @@ struct ddr_cmdtctrl {
unsigned int resv2[12];
unsigned int dt0ioctl;
unsigned int dt1ioctl;
unsigned int dt2ioctrl;
unsigned int dt3ioctrl;
unsigned int resv3[4];
unsigned int emif_sdram_config_ext;
};
struct ctrl_ioregs {
unsigned int cm0ioctl;
unsigned int cm1ioctl;
unsigned int cm2ioctl;
unsigned int dt0ioctl;
unsigned int dt1ioctl;
unsigned int dt2ioctrl;
unsigned int dt3ioctrl;
unsigned int emif_sdram_config_ext;
};
/**
* Configure DDR io control registers
*/
void config_io_ctrl(unsigned long val);
void config_io_ctrl(const struct ctrl_ioregs *ioregs);
struct ddr_ctrl {
unsigned int ddrioctrl;
@@ -291,8 +319,9 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
void config_ddr(unsigned int pll, unsigned int ioctrl,
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr);
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
#endif /* _DDR_DEFS_H */

1
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
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@@ -62,6 +62,7 @@
#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
#define CM_DEVICE_INST 0x44df4100
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)

12
arch/arm/include/asm/emif.h
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@@ -14,11 +14,15 @@
#define _EMIF_H_
#include <asm/types.h>
#include <common.h>
#include <asm/io.h>
/* Base address */
#define EMIF1_BASE 0x4c000000
#define EMIF2_BASE 0x4d000000
#define EMIF_4D 0x4
#define EMIF_4D5 0x5
/* Registers shifts, masks and values */
/* EMIF_MOD_ID_REV */
@@ -1148,6 +1152,14 @@ struct read_write_regs {
u32 write_reg;
};
static inline u32 get_emif_rev(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
>> EMIF_REG_MAJOR_REVISION_SHIFT;
}
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })