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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source
This commit is contained in:
Tom Rini
2020-04-20 08:45:27 -04:00
parent 8d5d3bcf3c 931edc6efb
commit d1bbf833aa
92 changed files with 3152 additions and 491 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/dts/Makefile
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@@ -620,12 +620,14 @@ dtb-y += \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-mba6a.dtb \
imx6dl-mba6b.dtb \
imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-pico.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revb1.dtb \
imx6dl-wandboard-revd1.dtb \
endif
@@ -649,6 +651,8 @@ dtb-y += \
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
imx6q-novena.dtb \
@@ -657,7 +661,7 @@ dtb-y += \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6q-tbs2910.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb \
imx6qp-wandboard-revd1.dtb \
@@ -728,7 +732,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-evk.dtb \
imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \

7
arch/arm/dts/imx53-kp-u-boot.dtsi
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@@ -5,6 +5,13 @@
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
&fec {
fixed-link { /* RMII fixed link for both HSC|DDC */
speed = <100>;
full-duplex;
};
};
&pmic {
u-boot,i2c-transaction-bytes = <3>;
};

6
arch/arm/dts/imx6dl-dhcom-pdk2-u-boot.dtsi Normal file
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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
*/
#include "imx6qdl-dhcom-pdk2-u-boot.dtsi"

18
arch/arm/dts/imx6dl-mba6.dtsi Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&ethphy {
rxdv-skew-ps = <180>;
txen-skew-ps = <0>;
rxd3-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd0-skew-ps = <180>;
txd3-skew-ps = <120>;
txd2-skew-ps = <0>;
txd1-skew-ps = <300>;
txd0-skew-ps = <120>;
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};

16
arch/arm/dts/imx6dl-mba6a.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S on MBa6x";
compatible = "tq,mba6a", "tq,tqma6dl", "fsl,imx6dl";
};

16
arch/arm/dts/imx6dl-mba6b.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S on MBa6x";
compatible = "tq,mba6b", "tq,tqma6dl", "fsl,imx6dl";
};

14
arch/arm/dts/imx6dl-tqma6a.dtsi Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x20000000>;
};
};

14
arch/arm/dts/imx6dl-tqma6b.dtsi Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x20000000>;
};
};

4
arch/arm/dts/imx6dl-wandboard-revb1.dts → arch/arm/dts/imx6dl-wandboard-revd1.dts
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@@ -6,10 +6,10 @@
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-wandboard-revb1.dtsi"
#include "imx6qdl-wandboard-revd1.dtsi"
/ {
model = "Wandboard i.MX6 Dual Lite Board rev B1";
model = "Wandboard i.MX6 Dual Lite Board revD1";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
memory@10000000 {

2
arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi
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@@ -3,6 +3,8 @@
* Copyright (C) 2019 Claudius Heine <ch@denx.de>
*/
#include "imx6qdl-dhcom-pdk2-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";

18
arch/arm/dts/imx6q-mba6.dtsi Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&ethphy {
rxdv-skew-ps = <180>;
txen-skew-ps = <120>;
rxd3-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd0-skew-ps = <180>;
txd3-skew-ps = <120>;
txd2-skew-ps = <0>;
txd1-skew-ps = <180>;
txd0-skew-ps = <360>;
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};

16
arch/arm/dts/imx6q-mba6a.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,mba6a", "fsl,imx6q";
};

16
arch/arm/dts/imx6q-mba6b.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,mba6b", "fsl,imx6q";
};

14
arch/arm/dts/imx6q-tqma6a.dtsi Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6q.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x40000000>;
};
};

14
arch/arm/dts/imx6q-tqma6b.dtsi Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6q.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x40000000>;
};
};

4
arch/arm/dts/imx6q-wandboard-revb1.dts → arch/arm/dts/imx6q-wandboard-revd1.dts
View File

@@ -6,10 +6,10 @@
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-wandboard-revb1.dtsi"
#include "imx6qdl-wandboard-revd1.dtsi"
/ {
model = "Wandboard i.MX6 Quad Board rev B1";
model = "Wandboard i.MX6 Quad Board revD1";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
memory@10000000 {

23
arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi Normal file
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@@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
*/
#include "imx6qdl-dhcom-u-boot.dtsi"
/ {
fec_vio: regulator-fec {
compatible = "regulator-fixed";
regulator-name = "fec-vio";
gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
};
&fec {
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <10>;
phy-supply = <&fec_vio>;
};

9
arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi Normal file
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@@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
*/
&reg_usb_otg_vbus {
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

207
arch/arm/dts/imx6qdl-mba6.dtsi Normal file
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@@ -0,0 +1,207 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/ {
aliases {
mmc1 = &usdhc2;
};
chosen {
linux,stdout-path = &uart2;
stdout-path = &uart2;
};
regulators {
reg_mba6_3p3v: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "supply-mba6-3p3v";
reg = <1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_otgvbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_otgpwr>;
regulator-name = "otg-vbus-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin_supply = <&reg_3p3v>;
};
};
};
&fec {
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <100>;
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <3>;
force-master;
max-speed = <1000>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
mba6 {
pinctrl_enet: enetgrp {
fsl,pins = <
/* FEC phy IRQ */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
/* FEC phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
/* DSE = 100, 100k up, SPEED = MED */
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
/* DSE = 111, pull 100k up */
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
/* DSE = 111, pull external */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */
/* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
>;
};
pinctrl_reg_otgpwr: regotgpwrgrp {
fsl,pins = <
/* OTG_PWR */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
>;
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
vbus-supply = <&reg_otgvbus>;
status = "okay";
};
&usdhc2 { /* Baseboard Slot */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_mba6_3p3v>;
bus-width = <4>;
no-1-8-v;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&wdog1 {
status = "okay";
};

39
arch/arm/dts/imx6qdl-mba6a.dtsi Normal file
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@@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c1 {
sensor1: lm75@49 {
compatible = "lm75";
reg = <0x49>;
};
eeprom1: m24c64@57 {
compatible = "st,24c64", "at24";
reg = <0x57>;
pagesize = <32>;
};
rtc1: ds1339@68 {
compatible = "ds1339";
reg = <0x68>;
};
};
&iomuxc {
mba6 {
pinctrl_enet_fix: enetfixgrp {
fsl,pins = <
/* ENET ping patch */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
};

45
arch/arm/dts/imx6qdl-mba6b.dtsi Normal file
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@@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c3 {
sensor1: lm75@49 {
compatible = "lm75";
reg = <0x49>;
};
eeprom1: m24c64@57 {
compatible = "st,24c64", "at24";
reg = <0x57>;
pagesize = <32>;
};
rtc1: ds1339@68 {
compatible = "ds1339";
reg = <0x68>;
};
};
&iomuxc {
mba6 {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
};
};

211
arch/arm/dts/imx6qdl-tqma6.dtsi Normal file
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@@ -0,0 +1,211 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/ {
aliases {
mmc0 = &usdhc3;
/delete-property/ mmc1;
/delete-property/ mmc2;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
reg = <0>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
status = "okay";
flash: m25p80@0 {
status = "okay";
compatible = "micron,n25q128a13", "n25q128a13";
spi-max-frequency = <50000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
};
};
&iomuxc {
tqma6 {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
};
pinctrl_i2c1_tqma6: i2c1-tqma6grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c3_tqma6: i2c3-tqma6grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
};
&pmic {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio6>;
interrupts = <10 8>;
regulators {
reg_vddcore: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v_600mA: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-always-on;
};
reg_snvs_3v: vsnvs {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
reg_vrefddr: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
/* not used */
};
reg_vgen2_1v2_eth: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen4_1v8: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_1v8_eth: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
non-removable;
disable-wp;
bus-width = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mmccard: mmccard@0 {
reg = <0>;
compatible = "mmc-card";
broken-hpi;
};
};

27
arch/arm/dts/imx6qdl-tqma6a.dtsi Normal file
View File

@@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_tqma6>;
clock-frequency = <100000>;
status = "okay";
pmic: pf0100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor0: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom0: m24c64@50 {
compatible = "st,24c64", "at24";
reg = <0x50>;
pagesize = <32>;
};
};

27
arch/arm/dts/imx6qdl-tqma6b.dtsi Normal file
View File

@@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_tqma6>;
clock-frequency = <100000>;
status = "okay";
pmic: pf0100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor0: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom0: m24c64@50 {
compatible = "st,24c64", "at24";
reg = <0x50>;
pagesize = <32>;
};
};

44
arch/arm/dts/imxrt1020-evk-u-boot.dtsi Normal file
View File

@@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
/ {
chosen {
u-boot,dm-spl;
};
};
&lpuart1 { /* console */
u-boot,dm-spl;
};
&semc {
bank1: bank@0 {
u-boot,dm-spl;
};
};
&iomuxc {
u-boot,dm-spl;
imxrt1020-evk {
u-boot,dm-spl;
pinctrl_lpuart1: lpuart1grp {
u-boot,dm-spl;
};
pinctrl_semc: semcgrp {
u-boot,dm-spl;
};
pinctrl_usdhc0: usdhc0grp {
u-boot,dm-spl;
};
};
};
&usdhc1 {
u-boot,dm-spl;
};

198
arch/arm/dts/imxrt1020-evk.dts Normal file
View File

@@ -0,0 +1,198 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
/dts-v1/;
#include "imxrt1020.dtsi"
#include "imxrt1020-evk-u-boot.dtsi"
#include <dt-bindings/pinctrl/pins-imxrt1020.h>
/ {
model = "NXP IMXRT1020-evk board";
compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x80000000 0x2000000>;
};
};
&lpuart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&semc {
/*
* Memory configuration from sdram datasheet IS42S16160J-6TLI
*/
fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
MUX_CSX0_SDRAM_CS1
0
0
0
0>;
fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
BL_8
COL_9BITS
CL_3>;
fsl,sdram-timing = /bits/ 8 <0x2
0x2
0x9
0x1
0x5
0x6
0x20
0x09
0x01
0x00
0x04
0x0A
0x21
0x50>;
bank1: bank@0 {
fsl,base-address = <0x80000000>;
fsl,memory-size = <MEM_SIZE_32M>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
imxrt1020-evk {
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
0xf1
MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
0xf1
>;
};
pinctrl_semc: semcgrp {
fsl,pins = <
MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
0xf1 /* SEMC_D0 */
MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
0xf1 /* SEMC_D1 */
MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
0xf1 /* SEMC_D2 */
MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
0xf1 /* SEMC_D3 */
MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
0xf1 /* SEMC_D4 */
MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
0xf1 /* SEMC_D5 */
MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
0xf1 /* SEMC_D6 */
MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
0xf1 /* SEMC_D7 */
MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
0xf1 /* SEMC_DM0 */
MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
0xf1 /* SEMC_CAS */
MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
0xf1 /* SEMC_RAS */
MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
0xf1 /* SEMC_CS0 */
MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
0xf1 /* SEMC_BA0 */
MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
0xf1 /* SEMC_BA1 */
MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
0xf1 /* SEMC_A10 */
MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
0xf1 /* SEMC_A1 */
MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
0xf1 /* SEMC_A2 */
MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
0xf1 /* SEMC_A3 */
MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
0xf1 /* SEMC_A4 */
MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
0xf1 /* SEMC_A5 */
MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
0xf1 /* SEMC_A6 */
MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
0xf1 /* SEMC_A7 */
MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
0xf1 /* SEMC_A8 */
MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
0xf1 /* SEMC_A9 */
MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
0xf1 /* SEMC_A11 */
MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
0xf1 /* SEMC_A12 */
MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
0xf1 /* SEMC_CKE */
MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
0xf1 /* SEMC_CLK */
MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
0xf1 /* SEMC_DM01 */
MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
0xf1 /* SEMC_D8 */
MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
0xf1 /* SEMC_D9 */
MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
0xf1 /* SEMC_D10 */
MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
0xf1 /* SEMC_D11 */
MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
0xf1 /* SEMC_D12 */
MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
0xf1 /* SEMC_D13 */
MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
0xf1 /* SEMC_D14 */
MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
0xf1 /* SEMC_D15 */
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
0x1B000
MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
0x17061
>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
status = "okay";
cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};

133
arch/arm/dts/imxrt1020.dtsi Normal file
View File

@@ -0,0 +1,133 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include "armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1020-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/memory/imxrt-sdram.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
mmc0 = &usdhc1;
serial0 = &lpuart1;
};
clocks {
u-boot,dm-spl;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
soc {
u-boot,dm-spl;
semc: semc@402f0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1020_CLK_SEMC>;
pinctrl-0 = <&pinctrl_semc>;
pinctrl-names = "default";
status = "okay";
};
lpuart1: serial@40184000 {
compatible = "fsl,imxrt-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1020_CLK_LPUART1>;
clock-names = "per";
status = "disabled";
};
iomuxc: iomuxc@401f8000 {
compatible = "fsl,imxrt-iomuxc";
reg = <0x401f8000 0x4000>;
fsl,mux_mask = <0x7>;
};
clks: ccm@400fc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
usdhc1: usdhc@402c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1020_CLK_USDHC1>;
clock-names = "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
gpio1: gpio@401b8000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@401bc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@401c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

60
arch/arm/dts/imxrt1050-evk.dts
View File

@@ -185,6 +185,33 @@
0x17061
>;
};
pinctrl_lcdif: lcdifgrp {
u-boot,dm-spl;
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
>;
};
};
};
@@ -198,3 +225,36 @@
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
status = "okay";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
display-timings {
timing0: timing0 {
clock-frequency = <9300000>;
hactive = <480>;
vactive = <272>;
hback-porch = <4>;
hfront-porch = <8>;
vback-porch = <4>;
vfront-porch = <8>;
hsync-len = <41>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};

14
arch/arm/dts/imxrt1050.dtsi
View File

@@ -4,7 +4,6 @@
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
@@ -12,7 +11,11 @@
#include <dt-bindings/memory/imxrt-sdram.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
display0 = &lcdif;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -142,5 +145,14 @@
interrupt-controller;
#interrupt-cells = <2>;
};
lcdif: lcdif@402b8000 {
compatible = "fsl,imxrt-lcdif";
reg = <0x402b8000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_LCDIF>;
clock-names = "per";
status = "disabled";
};
};
};

6
arch/arm/include/asm/arch-imxrt/imx-regs.h
View File

@@ -17,4 +17,10 @@
#define ANATOP_BASE_ADDR 0x400d8000
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#endif
#endif /* __ASM_ARCH_IMX_REGS_H__ */

19
arch/arm/include/asm/arch-mx6/mx6-ddr.h
View File

@@ -306,6 +306,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
/*
* NoC scheduler registers - only on IMX6DQP
*/
#define MX6DQP_NOC_SCHED_BASE 0x00bb0000
struct mx6dqp_noc_sched_regs {
u32 coreid;
u32 revid;
u32 ddrconf;
u32 ddrtiming;
u32 ddrmode;
u32 rlat;
u32 res1[4];
u32 ipu1;
u32 ipu2;
u32 res2[2];
u32 activate;
u32 res3[16];
};
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];

6
arch/arm/include/asm/mach-imx/regs-lcdif.h
View File

@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_IMX8M)
defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -49,7 +49,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
#if defined(CONFIG_MX23)
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_IMX8M)
defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */

9
arch/arm/mach-imx/imxrt/Kconfig
View File

@@ -3,6 +3,10 @@ if ARCH_IMXRT
config IMXRT
bool
config IMXRT1020
bool
select IMXRT
config IMXRT1050
bool
select IMXRT
@@ -14,12 +18,17 @@ choice
prompt "NXP i.MXRT board select"
optional
config TARGET_IMXRT1020_EVK
bool "Support imxrt1020 EVK board"
select IMXRT1020
config TARGET_IMXRT1050_EVK
bool "Support imxrt1050 EVK board"
select IMXRT1050
endchoice
source "board/freescale/imxrt1020-evk/Kconfig"
source "board/freescale/imxrt1050-evk/Kconfig"
endif

11
arch/arm/mach-imx/mx6/Kconfig
View File

@@ -590,7 +590,18 @@ config TARGET_KP_IMX6Q_TPC
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select MXC_SPI
select SPI
imply DM
imply DM_GPIO
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply DM_I2C
imply CMD_SF
imply CMD_DM
config TARGET_UDOO
bool "udoo"

96
arch/arm/mach-imx/mx6/ddr.c
View File

@@ -945,6 +945,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
#define BOOT_CFG3_DDR_MASK 0x30
#define BOOT_CFG3_EXT_DDR_MASK 0x33
#define DDR_MMAP_NOC_SINGLE 0
#define DDR_MMAP_NOC_DUAL 0x31
/* NoC ACTIVATE shifts */
#define NOC_RD_SHIFT 0
#define NOC_FAW_PERIOD_SHIFT 4
#define NOC_FAW_BANKS_SHIFT 10
/* NoC DdrTiming shifts */
#define NOC_ACT_TO_ACT_SHIFT 0
#define NOC_RD_TO_MISS_SHIFT 6
#define NOC_WR_TO_MISS_SHIFT 12
#define NOC_BURST_LEN_SHIFT 18
#define NOC_RD_TO_WR_SHIFT 21
#define NOC_WR_TO_RD_SHIFT 26
#define NOC_BW_RATIO_SHIFT 31
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@@ -1234,6 +1255,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -1526,6 +1549,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
/*
* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
* configure it and disable MMDC arbitration/reordering (see EB828)
*/
if (is_mx6dqp() &&
((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
(soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
struct mx6dqp_noc_sched_regs *noc_sched =
(struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
/*
* These values are fixed based on integration parameters and
* should not be modified
*/
noc_sched->rlat = 0x00000040;
noc_sched->ipu1 = 0x00000020;
noc_sched->ipu2 = 0x00000020;
noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
(tfaw << NOC_FAW_PERIOD_SHIFT) |
(trrd << NOC_RD_SHIFT);
noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
<< NOC_BW_RATIO_SHIFT) |
((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
(4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
((tcwl + twr + trp + trcd)
<< NOC_WR_TO_MISS_SHIFT) |
((trtp + trp + trcd - 4)
<< NOC_RD_TO_MISS_SHIFT) |
(trc << NOC_ACT_TO_ACT_SHIFT);
if (sysinfo->dsize == 2) {
if (ddr3_cfg->coladdr == 10) {
if (ddr3_cfg->rowaddr == 15 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 4;
else
noc_sched->ddrconf = 0;
} else if (ddr3_cfg->coladdr == 11) {
noc_sched->ddrconf = 1;
}
} else {
if (ddr3_cfg->coladdr == 9) {
if (ddr3_cfg->rowaddr == 13)
noc_sched->ddrconf = 2;
else if (ddr3_cfg->rowaddr == 14)
noc_sched->ddrconf = 15;
} else if (ddr3_cfg->coladdr == 10) {
if (ddr3_cfg->rowaddr == 14 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 14;
else if (ddr3_cfg->rowaddr == 15 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 9;
else
noc_sched->ddrconf = 3;
} else if (ddr3_cfg->coladdr == 11) {
if (ddr3_cfg->rowaddr == 15 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 4;
else
noc_sched->ddrconf = 0;
} else if (ddr3_cfg->coladdr == 12) {
if (ddr3_cfg->rowaddr == 14)
noc_sched->ddrconf = 1;
}
}
/* Disable MMDC arbitration/reordering */
mmdc0->maarcr = 0x14420000;
}
/* Step 13: Deassert config request - init complete */
mmdc0->mdscr = 0x00000000;

29
arch/arm/mach-imx/mx7ulp/soc.c
View File

@@ -118,12 +118,26 @@ void init_wdog(void)
disable_wdog(WDG2_RBASE);
}
static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
if (reg & PMC0_CTRL_LDOEN)
return true;
else
return false;
}
#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
unsigned int reg;
if (ldo_mode_is_enabled())
return;
/* Set LDOOKDIS */
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
@@ -193,21 +207,6 @@ const char *get_imx_type(u32 imxtype)
return "7ULP";
}
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
#define PMC0_CTRL_LDOEN BIT(31)
static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
if (reg & PMC0_CTRL_LDOEN)
return true;
else
return false;
}
int print_cpuinfo(void)
{
u32 cpurev;