mirror of
https://xff.cz/git/u-boot/
synced 2025-09-01 08:42:12 +02:00
arm: add support for SoC s5p4418 (cpu) / nanopi2 board
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - SPL not supported yet --> no spl-dir in arch/arm/cpu/armv7/s5p4418/. Appropriate line in Makefile removed. - cpu.c: '#include <cpu_func.h>' added. - arch/arm/cpu/armv7/s5p4418/u-boot.lds removed, is not required anylonger. - "obj-$(CONFIG_ARCH_NEXELL) += s5p-common/" added to arch/arm/cpu/armv7/Makefile since s5p-common/pwm.c is used instead of drivers/pwm/pwm-nexell.c. - s5p4418.dtsi: '#include "../../../include/generated/autoconf.h"' removed, is not necessary, error at out-of-tree building. '#ifdef CONFIG_CPU_NXP4330'-blocks (2x) removed. Some minor changes regarding mmc. 'u-boot,dm-pre-reloc' added to dp0 because of added DM_VIDEO support. - board/s5p4418/ renamed to board/friendlyarm/ - All s5p4418-boards except nanopi2 removed because there is no possibility to test the other boards. - Kconfig: Changes to have a structure like mach-bcm283x (RaspberryPi), e.g. "config ..." entries moved from/to other Kconfig. - "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. - nanopi2/board.c: All getenv(), getenv_ulong(), setenv() and saveenv() renamed to env_get(), env_get_ulong(), env_set() and env_save(), respectively. MACH_TYPE_S5P4418 is not defined anymore, therefore appropriate code removed (not necessary for DT-kernels). - nanopi2/onewire.c: All crc8() renamed to crc8_ow() because crc8() is already defined in lib/crc8.c (with different parameters). - dts: "nexell,s5pxx18-i2c" used instead of "i2c-gpio", i2c0 and i2c1 added. gmac-, ehci- and dwc2otg-entries removed because the appropriate functionality is not supported yet. New mmc-property "mmcboost" added. s5p4418-pinctrl.dtsi: gmac-entries removed, mmc- and i2c-entries added. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
This commit is contained in:
Stefan Bosch
Tom Rini
@@ -42,3 +42,5 @@ obj-$(CONFIG_RMOBILE) += rmobile/
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obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-$(CONFIG_VF610) += vf610/
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obj-$(CONFIG_ARCH_S5P4418) += s5p4418/
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obj-$(CONFIG_ARCH_NEXELL) += s5p-common/
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6
arch/arm/cpu/armv7/s5p4418/Makefile
Normal file
6
arch/arm/cpu/armv7/s5p4418/Makefile
Normal file
@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2016 Nexell
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# Hyunseok, Jung <hsjung@nexell.co.kr>
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obj-y += cpu.o
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121
arch/arm/cpu/armv7/s5p4418/cpu.c
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121
arch/arm/cpu/armv7/s5p4418/cpu.c
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@@ -0,0 +1,121 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* Hyunseok, Jung <hsjung@nexell.co.kr>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/tieoff.h>
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#include <cpu_func.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_ARCH_CPU_INIT
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#error must be define the macro "CONFIG_ARCH_CPU_INIT"
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#endif
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void s_init(void)
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{
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}
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static void cpu_soc_init(void)
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{
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/*
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* NOTE> ALIVE Power Gate must enable for Alive register access.
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* must be clear wfi jump address
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*/
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writel(1, ALIVEPWRGATEREG);
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writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
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/* write 0xf0 on alive scratchpad reg for boot success check */
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writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
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/* set l2 cache tieoff */
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nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
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nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
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}
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#ifdef CONFIG_PL011_SERIAL
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static void serial_device_init(void)
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{
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char dev[10];
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int id;
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sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
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id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
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struct clk *clk = clk_get((const char *)dev);
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/* reset control: Low active ___|--- */
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nx_rstcon_setrst(id, RSTCON_ASSERT);
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udelay(10);
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nx_rstcon_setrst(id, RSTCON_NEGATE);
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udelay(10);
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/* set clock */
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clk_disable(clk);
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clk_set_rate(clk, CONFIG_PL011_CLOCK);
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clk_enable(clk);
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}
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#endif
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int arch_cpu_init(void)
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{
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flush_dcache_all();
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cpu_soc_init();
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clk_init();
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if (IS_ENABLED(CONFIG_PL011_SERIAL))
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serial_device_init();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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return 0;
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}
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#endif
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void reset_cpu(ulong ignored)
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{
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void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
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const u32 sw_rst_enb_bitpos = 3;
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const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
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const u32 sw_rst_bitpos = 12;
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const u32 sw_rst_mask = 1 << sw_rst_bitpos;
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int pwrcont = 0x224;
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int pwrmode = 0x228;
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u32 read_value;
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read_value = readl((void *)(clkpwr_reg + pwrcont));
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read_value &= ~sw_rst_enb_mask;
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read_value |= 1 << sw_rst_enb_bitpos;
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writel(read_value, (void *)(clkpwr_reg + pwrcont));
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writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
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}
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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@@ -147,6 +147,9 @@ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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rv1108-elgin-r1.dtb \
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rv1108-evb.dtb
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dtb-$(CONFIG_ARCH_S5P4418) += \
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s5p4418-nanopi2.dtb
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dtb-$(CONFIG_ARCH_MESON) += \
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meson-gxbb-nanopi-k2.dtb \
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meson-gxbb-odroidc2.dtb \
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110
arch/arm/dts/s5p4418-nanopi2.dts
Normal file
110
arch/arm/dts/s5p4418-nanopi2.dts
Normal file
@@ -0,0 +1,110 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
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*
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* (C) Copyright 2017 FriendlyElec Computer Tech. Co., Ltd.
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* (http://www.friendlyarm.com)
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*
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* (C) Copyright 2016 Nexell
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* Youngbok, Park <park@nexell.co.kr>
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*/
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/dts-v1/;
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#include "s5p4418.dtsi"
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/ {
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model = "FriendlyElec boards based on Nexell s5p4418";
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cpu-model = "S5p4418";
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compatible = "friendlyelec,nanopi2",
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"nexell,s5p4418";
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aliases {
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mmc0 = "/mmc@c0069000";
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mmc1 = "/mmc@c0062000";
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i2c0 = "/i2c@c00a4000";
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i2c1 = "/i2c@c00a5000";
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i2c2 = "/i2c@c00a6000";
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};
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mmc0:mmc@c0062000 {
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frequency = <50000000>;
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drive_dly = <0x0>;
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drive_shift = <0x03>;
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sample_dly = <0x00>;
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sample_shift = <0x02>;
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mmcboost = <0>;
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status = "okay";
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};
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mmc2:mmc@c0069000 {
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frequency = <50000000>;
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drive_dly = <0x0>;
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drive_shift = <0x03>;
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sample_dly = <0x00>;
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sample_shift = <0x02>;
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mmcboost = <0>;
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status = "okay";
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};
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/* NanoPi2: Header "CON2", NanoPC-T2: EEPROM (MAC-Addr.) and Audio */
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i2c0:i2c@c00a4000 {
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status ="okay";
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};
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/* NanoPi2: Header "CON2" and HDMI, NanoPC-T2: HDMI */
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i2c1:i2c@c00a5000 {
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status ="okay";
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};
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/* NanoPi2: LCD interface, NanoPC-T2: LCD, LVDS and MIPI interfaces */
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i2c2:i2c@c00a6000 {
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status ="okay";
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};
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dp0:dp@c0102800 {
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status = "okay";
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module = <0>;
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lcd-type = "lvds";
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dp-device {
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format = <0>; /* 0:VESA, 1:JEIDA */
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};
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dp-sync {
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h_active_len = <1024>;
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h_front_porch = <84>;
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h_back_porch = <84>;
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h_sync_width = <88>;
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h_sync_invert = <0>;
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v_active_len = <600>;
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v_front_porch = <10>;
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v_back_porch = <10>;
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v_sync_width = <20>;
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v_sync_invert = <0>;
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};
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dp-ctrl {
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clk_src_lv0 = <3>;
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clk_div_lv0 = <16>;
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clk_src_lv1 = <7>;
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clk_div_lv1 = <1>;
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out_format = <2>;
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};
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dp-planes {
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layer_top {
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screen_width = <1024>;
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screen_height = <600>;
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back_color = <0x0>;
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};
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layer_1 { /* RGB 1 */
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width = <1024>;
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height = <600>;
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format = <0x06530000>;
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pixel_byte = <4>;
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};
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};
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};
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};
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135
arch/arm/dts/s5p4418-pinctrl.dtsi
Normal file
135
arch/arm/dts/s5p4418-pinctrl.dtsi
Normal file
@@ -0,0 +1,135 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Nexell's s5p6818 SoC pin-mux and pin-config device tree source
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*
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* (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
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*
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* Copyright (C) 2016 Nexell Co., Ltd.
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* http://www.nexell.co.kr
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*
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* Nexell's s5p6818 SoC pin-mux and pin-config options are listed as
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* device tree nodes in this file.
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*/
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pinctrl@C0010000 {
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/*
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* values for "pin-pull":
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* pulldown resistor = 0
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* pullup = 1
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* no pullup/down = 2
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*/
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/* MMC */
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mmc0_clk: mmc0-clk {
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pins = "gpioa-29";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <2>;
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};
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mmc0_cmd: mmc0-cmd {
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pins = "gpioa-31";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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mmc0_bus4: mmc0-bus-width4 {
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pins = "gpiob-1, gpiob-3, gpiob-5, gpiob-7";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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mmc1_clk: mmc1-clk {
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pins = "gpiod-22";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <2>;
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};
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mmc1_cmd: mmc1-cmd {
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pins = "gpiod-23";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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mmc1_bus4: mmc1-bus-width4 {
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pins = "gpiod-24, gpiod-25, gpiod-26, gpiod-27";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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mmc2_clk: mmc2-clk {
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pins = "gpioc-18";
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pin-function = <2>;
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pin-pull = <2>;
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pin-strength = <2>;
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};
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mmc2_cmd: mmc2-cmd {
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pins = "gpioc-19";
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pin-function = <2>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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mmc2_bus4: mmc2-bus-width4 {
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pins = "gpioc-20, gpioc-21, gpioc-22, gpioc-23";
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pin-function = <2>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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mmc2_bus8: mmc2-bus-width8 {
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nexell,pins = "gpioe-21", "gpioe-22", "gpioe-23", "gpioe-24";
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pin-function = <2>;
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pin-pull = <2>;
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pin-strength = <1>;
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};
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/* I2C */
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i2c0_sda:i2c0-sda {
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pins = "gpiod-3";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <0>;
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};
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i2c0_scl:i2c0-scl {
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pins = "gpiod-2";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <0>;
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};
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i2c1_sda:i2c1-sda {
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pins = "gpiod-5";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <0>;
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};
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i2c1_scl:i2c1-scl {
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pins = "gpiod-4";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <0>;
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};
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i2c2_sda:i2c2-sda {
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pins = "gpiod-7";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <0>;
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};
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i2c2_scl:i2c2-scl {
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pins = "gpiod-6";
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pin-function = <1>;
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pin-pull = <2>;
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pin-strength = <0>;
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};
|
||||
};
|
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170
arch/arm/dts/s5p4418.dtsi
Normal file
170
arch/arm/dts/s5p4418.dtsi
Normal file
@@ -0,0 +1,170 @@
|
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// SPDX-License-Identifier: GPL-2.0+
|
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/*
|
||||
* (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
|
||||
*
|
||||
* (C) Copyright 2016 Nexell
|
||||
* Youngbok, Park <park@nexell.co.kr>
|
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*
|
||||
*/
|
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#include "skeleton.dtsi"
|
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|
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/ {
|
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#include "s5p4418-pinctrl.dtsi"
|
||||
|
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aliases {
|
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mmc0 = &mmc0;
|
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mmc1 = &mmc1;
|
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mmc2 = &mmc2;
|
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gmac = "/ethernet@c0060000";
|
||||
};
|
||||
|
||||
mmc2:mmc@c0069000 {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
compatible = "nexell,nexell-dwmmc";
|
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reg = <0xc0069000 0x1000>;
|
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bus-width = <4>;
|
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index = <2>;
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max-frequency = <50000000>;
|
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pinctrl-names = "default";
|
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pinctrl-0 = <&mmc2_clk>, <&mmc2_cmd>, <&mmc2_bus4>;
|
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status = "disabled";
|
||||
};
|
||||
|
||||
mmc1:mmc@c0068000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nexell,nexell-dwmmc";
|
||||
reg = <0xc0068000 0x1000>;
|
||||
bus-width = <4>;
|
||||
index = <1>;
|
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max-frequency = <50000000>;
|
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_clk>, <&mmc1_cmd>, <&mmc1_bus4>;
|
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status = "disabled";
|
||||
};
|
||||
|
||||
mmc0:mmc@c0062000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nexell,nexell-dwmmc";
|
||||
reg = <0xc0062000 0x1000>;
|
||||
bus-width = <4>;
|
||||
index = <0>;
|
||||
max-frequency = <50000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_clk>, <&mmc0_cmd>, <&mmc0_bus4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0:i2c@c00a4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nexell,s5pxx18-i2c";
|
||||
reg = <0xc00a4000 0x100>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_sda>, <&i2c0_scl>;
|
||||
status ="disabled";
|
||||
};
|
||||
|
||||
i2c1:i2c@c00a5000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nexell,s5pxx18-i2c";
|
||||
reg = <0xc00a5000 0x100>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_sda>, <&i2c1_scl>;
|
||||
status ="disabled";
|
||||
};
|
||||
|
||||
i2c2:i2c@c00a6000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nexell,s5pxx18-i2c";
|
||||
reg = <0xc00a6000 0x100>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_sda>, <&i2c2_scl>;
|
||||
status ="disabled";
|
||||
};
|
||||
|
||||
dp0:dp@c0102800 {
|
||||
compatible = "nexell,nexell-display";
|
||||
reg = <0xc0102800 0x100>;
|
||||
index = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp1:dp@c0102c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nexell,nexell-display";
|
||||
reg = <0xc0102c00 0x100>;
|
||||
index = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_a:gpio@c001a000 {
|
||||
compatible = "nexell,nexell-gpio";
|
||||
reg = <0xc001a000 0x00000010>;
|
||||
altr,gpio-bank-width = <32>;
|
||||
gpio-bank-name = "gpio_a";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_b:gpio@c001b000 {
|
||||
compatible = "nexell,nexell-gpio";
|
||||
reg = <0xc001b000 0x00000010>;
|
||||
altr,gpio-bank-width = <32>;
|
||||
gpio-bank-name = "gpio_b";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_c:gpio@c001c000 {
|
||||
compatible = "nexell,nexell-gpio";
|
||||
reg = <0xc001c000 0x00000010>;
|
||||
nexell,gpio-bank-width = <32>;
|
||||
gpio-bank-name = "gpio_c";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_d:gpio@c001d000 {
|
||||
compatible = "nexell,nexell-gpio";
|
||||
reg = <0xc001d000 0x00000010>;
|
||||
nexell,gpio-bank-width = <32>;
|
||||
gpio-bank-name = "gpio_d";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_e:gpio@c001e000 {
|
||||
compatible = "nexell,nexell-gpio";
|
||||
reg = <0xc001e000 0x00000010>;
|
||||
nexell,gpio-bank-width = <32>;
|
||||
gpio-bank-name = "gpio_e";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_alv:gpio@c0010800 {
|
||||
compatible = "nexell,nexell-gpio";
|
||||
reg = <0xc0010800 0x00000010>;
|
||||
nexell,gpio-bank-width = <32>;
|
||||
gpio-bank-name = "gpio_alv";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pinctrl@C0010000 {
|
||||
compatible = "nexell,s5pxx18-pinctrl";
|
||||
reg = <0xc0010000 0xf000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user