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imx6dl/imx6qdl: synchronise device trees with linux

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Synchronise device trees with linux-next next-20220708.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler
2022-07-21 15:27:26 +02:00
committed by Stefano Babic
parent 50b229523b
commit d0399a46e7
78 changed files with 3983 additions and 1323 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/dts/imx6-logicpd-baseboard.dtsi
View File

@@ -212,6 +212,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@@ -237,7 +238,6 @@
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
@@ -249,9 +249,9 @@
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
@@ -328,6 +328,10 @@
pinctrl-0 = <&pinctrl_pwm3>;
};
&snvs_pwrkey {
status = "okay";
};
&ssi2 {
status = "okay";
};
@@ -379,7 +383,7 @@
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
>;
};

4
arch/arm/dts/imx6-logicpd-som.dtsi
View File

@@ -207,6 +207,10 @@
vin-supply = <&sw1c_reg>;
};
&snvs_poweroff {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;

273
arch/arm/dts/imx6dl-mamoj.dts
View File

@@ -12,6 +12,156 @@
/ {
model = "BTicino i.MX6DL Mamoj board";
compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0>;
};
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */
brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>;
default-brightness-level = <7>;
};
display: disp0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_lcdif>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel-lcd {
compatible = "rocktech,rk070er9427";
backlight = <&backlight_lcd>;
power-supply = <&reg_lcd_lr>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
reg_lcd_3v3: regulator-lcd-dvdd {
compatible = "regulator-fixed";
regulator-name = "lcd-dvdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 1 0>;
enable-active-high;
startup-delay-us = <21000>;
};
reg_lcd_power: regulator-lcd-power {
compatible = "regulator-fixed";
regulator-name = "lcd-enable";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 6 0>;
enable-active-high;
vin-supply = <&reg_lcd_3v3>;
};
reg_lcd_vgl: regulator-lcd-vgl {
compatible = "regulator-fixed";
regulator-name = "lcd-vgl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
startup-delay-us = <6000>;
enable-active-high;
vin-supply = <&reg_lcd_power>;
};
reg_lcd_vgh: regulator-lcd-vgh {
compatible = "regulator-fixed";
regulator-name = "lcd-vgh";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
startup-delay-us = <6000>;
enable-active-high;
vin-supply = <&reg_lcd_avdd>;
};
reg_lcd_vcom: regulator-lcd-vcom {
compatible = "regulator-fixed";
regulator-name = "lcd-vcom";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>;
startup-delay-us = <11000>;
enable-active-high;
vin-supply = <&reg_lcd_vgh>;
};
reg_lcd_lr: regulator-lcd-lr {
compatible = "regulator-fixed";
regulator-name = "lcd-lr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_lcd_vcom>;
};
reg_lcd_avdd: regulator-lcd-avdd {
compatible = "regulator-fixed";
regulator-name = "lcd-avdd";
regulator-min-microvolt = <10280000>;
regulator-max-microvolt = <10280000>;
gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
startup-delay-us = <6000>;
enable-active-high;
vin-supply = <&reg_lcd_vgl>;
};
reg_usb_host: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usbhost-vbus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhost>;
regulator-min-microvolt = <50000000>;
regulator-max-microvolt = <50000000>;
gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_wl18xx_vmmc: regulator-wl18xx-vmcc {
compatible = "regulator-fixed";
regulator-name = "vwl1807";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
};
&fec {
@@ -34,7 +184,7 @@
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pmic: pfuze100@08 {
pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@@ -148,12 +298,57 @@
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_host>;
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
vmmc-supply = <&reg_wl18xx_vmmc>;
no-1-8-v;
non-removable;
wakeup-source;
keep-power-in-suspend;
cap-power-off-card;
max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
tcxo-clock-frequency = <26000000>;
};
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
@@ -201,6 +396,59 @@
>;
};
pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */
MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */
MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
@@ -208,6 +456,23 @@
>;
};
pinctrl_usbhost: usbhostgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -222,4 +487,10 @@
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0
>;
};
};

10
arch/arm/dts/imx6dl-mba6.dtsi
View File

@@ -1,6 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
&ethphy {
rxdv-skew-ps = <180>;

15
arch/arm/dts/imx6dl-mba6a.dts
View File

@@ -1,6 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
@@ -11,6 +15,7 @@
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S on MBa6x";
compatible = "tq,mba6a", "tq,tqma6dl", "fsl,imx6dl";
model = "TQ TQMa6S/DL on MBa6x";
compatible = "tq,imx6dl-mba6x-a", "tq,mba6a",
"tq,imx6dl-tqma6dl-a", "fsl,imx6dl";
};

15
arch/arm/dts/imx6dl-mba6b.dts
View File

@@ -1,6 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
@@ -11,6 +15,7 @@
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S on MBa6x";
compatible = "tq,mba6b", "tq,tqma6dl", "fsl,imx6dl";
model = "TQ TQMa6S/DL on MBa6x";
compatible = "tq,imx6dl-mba6x-b", "tq,mba6b",
"tq,imx6dl-tqma6dl-b", "fsl,imx6dl";
};

12
arch/arm/dts/imx6dl-nitrogen6x.dts
View File

@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013-2019 Boundary Devices, Inc.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2013 Boundary Devices, Inc.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-nitrogen6x.dtsi"

7
arch/arm/dts/imx6dl-pinfunc.h
View File

@@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6DL_PINFUNC_H
@@ -668,6 +664,7 @@
#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0
#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0

2
arch/arm/dts/imx6dl-riotboard.dts
View File

@@ -106,6 +106,8 @@
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
qca,smarteee-tw-us-1g = <24>;
qca,clk-out-frequency = <125000000>;
};
};
};

15
arch/arm/dts/imx6dl-sabreauto.dts
View File

@@ -11,3 +11,18 @@
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
};
&cpu0 {
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1200000
792000 1175000
396000 1175000
>;
};

12
arch/arm/dts/imx6dl-tqma6a.dtsi
View File

@@ -1,14 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
};

12
arch/arm/dts/imx6dl-tqma6b.dtsi
View File

@@ -1,14 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
};

15
arch/arm/dts/imx6dl.dtsi
View File

@@ -15,7 +15,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
@@ -44,6 +44,8 @@
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
cpu@1 {
@@ -64,6 +66,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -77,7 +80,7 @@
};
};
soc {
soc: soc {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
@@ -85,10 +88,6 @@
};
aips1: bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -295,6 +294,10 @@
compatible = "fsl,imx6dl-hdmi";
};
&iomuxc {
compatible = "fsl,imx6dl-iomuxc";
};
&ipu1_csi1 {
ipu1_csi1_from_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;

19
arch/arm/dts/imx6q-b450v3.dts
View File

@@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2015 Timesys Corporation.
* Copyright 2015 General Electric Company
@@ -66,13 +65,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ldb {
status = "okay";
@@ -92,14 +84,19 @@
};
&pca9539 {
P04 {
gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN",
"", "SM_D_ACT", "DP1_RST#", "",
"WD15S_EN", "WD15S_DIS#", "", "",
"", "", "", "";
P04-hog {
gpio-hog;
gpios = <4 0>;
output-low;
line-name = "PCA9539-P04";
};
P07 {
P07-hog {
gpio-hog;
gpios = <7 0>;
output-low;
@@ -158,5 +155,3 @@
};
};
};
#include "imx6q-bx50v3-uboot.dtsi"

17
arch/arm/dts/imx6q-b650v3.dts
View File

@@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2015 Timesys Corporation.
* Copyright 2015 General Electric Company
@@ -66,13 +65,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ldb {
status = "okay";
@@ -92,7 +84,12 @@
};
&pca9539 {
P07 {
gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN",
"", "SM_D_ACT", "DP1_RST#", "",
"WD15S_EN", "WD15S_DIS#", "", "",
"", "", "", "";
P07-hog {
gpio-hog;
gpios = <7 0>;
output-low;
@@ -157,5 +154,3 @@
};
};
};
#include "imx6q-bx50v3-uboot.dtsi"

23
arch/arm/dts/imx6q-b850v3.dts
View File

@@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2015 Timesys Corporation.
* Copyright 2015 General Electric Company
@@ -54,17 +53,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&ldb {
fsl,dual-channel;
status = "okay";
@@ -211,14 +199,19 @@
};
&pca9539 {
P10 {
gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN",
"REMOTE_ON_PML#", "SM_D_ACT", "DP1_RST#", "DP2_RST#",
"", "", "", "",
"", "", "", "";
P10-hog {
gpio-hog;
gpios = <8 0>;
output-low;
line-name = "PCA9539-P10";
};
P11 {
P11-hog {
gpio-hog;
gpios = <9 0>;
output-low;
@@ -300,5 +293,3 @@
phy-handle = <&switchphy4>;
};
};
#include "imx6q-bx50v3-uboot.dtsi"

18
arch/arm/dts/imx6q-ba16.dtsi
View File

@@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Support for imx6 based Advantech DMS-BA16 Qseven module
*
@@ -125,6 +124,9 @@
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-0 = <&pinctrl_usbotg_vbus>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@@ -135,12 +137,12 @@
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: n25q032@0 {
flash: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
@@ -173,8 +175,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
phy-supply = <&reg_3p3v>;
phy-handle = <&phy0>;
status = "okay";
mdio {
#address-cells = <1>;
@@ -346,6 +349,7 @@
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -586,6 +590,12 @@
>;
};
pinctrl_usbotg_vbus: usbotgvbusgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059

14
arch/arm/dts/imx6q-bosch-acc.dts
View File

@@ -554,13 +554,23 @@
status = "okay";
};
&usbphynop1 {
clocks = <&clks IMX6QDL_CLK_USBPHY1>;
clock-names = "main_clk";
vcc-supply = <&reg_usb_h1_vbus>;
};
&usbphynop2 {
vcc-supply = <&reg_usb_h2_vbus>;
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
wakeup-source;
voltage-ranges = <3300 3300>;
vmmc-supply = <&reg_sw4>;
fsl,wp-controller;
@@ -584,7 +594,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
fsl,ext-reset-output;
timeout-sec=<10>;
timeout-sec = <10>;
status = "okay";
};

61
arch/arm/dts/imx6q-bx50v3.dtsi
View File

@@ -1,4 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2015 Timesys Corporation.
* Copyright 2015 General Electric Company
@@ -103,10 +102,15 @@
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch: switch@0 {
compatible = "marvell,mv88e6085"; /* 88e6240*/
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -118,22 +122,32 @@
switchphy0: switchphy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy1: switchphy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy2: switchphy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy3: switchphy@3 {
reg = <3>;
interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy4: switchphy@4 {
reg = <4>;
interrupt-parent = <&switch>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
@@ -141,12 +155,12 @@
};
&ecspi5 {
cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
m25_eeprom: m25p80@0 {
m25_eeprom: flash@0 {
compatible = "atmel,at25";
spi-max-frequency = <10000000>;
size = <0x8000>;
@@ -159,8 +173,8 @@
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
pca9547: mux@70 {
compatible = "nxp,pca9547";
@@ -234,42 +248,42 @@
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
P12 {
P12-hog {
gpio-hog;
gpios = <10 0>;
output-low;
line-name = "PCA9539-P12";
};
P13 {
P13-hog {
gpio-hog;
gpios = <11 0>;
output-low;
line-name = "PCA9539-P13";
};
P14 {
P14-hog {
gpio-hog;
gpios = <12 0>;
output-low;
line-name = "PCA9539-P14";
};
P15 {
P15-hog {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "PCA9539-P15";
};
P16 {
P16-hog {
gpio-hog;
gpios = <14 0>;
output-low;
line-name = "PCA9539-P16";
};
P17 {
P17-hog {
gpio-hog;
gpios = <15 0>;
output-low;
@@ -301,15 +315,15 @@
&i2c2 {
pinctrl-names = "default", "gpio";
pinctrl-1 = <&pinctrl_i2c2_gpio>;
sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c3 {
pinctrl-names = "default", "gpio";
pinctrl-1 = <&pinctrl_i2c3_gpio>;
sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&iomuxc {
@@ -379,4 +393,17 @@
};
};
#include "imx6q-bx50v3-uboot.dtsi"
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
};

112
arch/arm/dts/imx6q-cm-fx6.dts
View File

@@ -43,13 +43,15 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
#include "imx6q.dtsi"
/ {
model = "CompuLab CM-FX6";
compatible = "compulab,cm-fx6", "fsl,imx6q";
memory {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
@@ -134,10 +136,35 @@
};
};
/*
* The U-Boot: audio mux node has been removed because the required dt-bindings
* header file is not present in the U-Boot.
*/
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
ssi2 {
fsl,audmux-port = <1>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_RCLKDIR |
IMX_AUDMUX_V2_PTCR_RCSEL(3 | 0x8) |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(3))
IMX_AUDMUX_V2_PDCR_RXDSEL(3)
>;
};
audmux4 {
fsl,audmux-port = <3>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(1) |
IMX_AUDMUX_V2_PTCR_RCLKDIR |
IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(1))
IMX_AUDMUX_V2_PDCR_RXDSEL(1)
>;
};
};
&cpu0 {
/*
@@ -161,13 +188,79 @@
>;
};
&cpu1 {
/*
* Although the imx6q fuse indicates that 1.2GHz operation is possible,
* the module behaves unstable at this frequency. Hence, remove the
* 1.2GHz operation point here.
*/
operating-points = <
/* kHz uV */
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
};
&cpu2 {
/*
* Although the imx6q fuse indicates that 1.2GHz operation is possible,
* the module behaves unstable at this frequency. Hence, remove the
* 1.2GHz operation point here.
*/
operating-points = <
/* kHz uV */
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
};
&cpu3 {
/*
* Although the imx6q fuse indicates that 1.2GHz operation is possible,
* the module behaves unstable at this frequency. Hence, remove the
* 1.2GHz operation point here.
*/
operating-points = <
/* kHz uV */
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
m25p80@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p", "jedec,spi-nor";
@@ -396,8 +489,3 @@
*/
status = "disabled";
};
/* The U-Boot: enable usdhc3 for mmc boot */
&usdhc3 {
status = "okay";
};

28
arch/arm/dts/imx6q-icore-ofcap10.dts
View File

@@ -12,6 +12,17 @@
/ {
model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit";
compatible = "engicam,imx6-icore", "fsl,imx6q";
panel {
compatible = "ampire,am-1280800n3tzqw-t00h";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ldb {
@@ -22,18 +33,11 @@
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <60000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <40>;
hfront-porch = <40>;
vback-porch = <10>;
vfront-porch = <3>;
hsync-len = <80>;
vsync-len = <10>;
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};

18
arch/arm/dts/imx6q-logicpd.dts
View File

@@ -9,11 +9,11 @@
/ {
model = "Logic PD i.MX6QD SOM-M3";
compatible = "fsl,imx6q";
compatible = "logicpd,imx6q-logicpd", "fsl,imx6q";
backlight: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000>;
pwms = <&pwm3 0 20000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&reg_lcd>;
@@ -21,6 +21,8 @@
panel-lvds0 {
compatible = "okaya,rs800480t-7x0gp";
power-supply = <&reg_lcd_reset>;
backlight = <&backlight>;
port {
panel_in_lvds0: endpoint {
@@ -38,7 +40,6 @@
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_3v3>;
startup-delay-us = <500000>;
};
@@ -52,7 +53,6 @@
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_lcd>;
};
};
@@ -73,6 +73,16 @@
status = "okay";
};
&i2c1 {
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
};
};
&ldb {
status = "okay";

2
arch/arm/dts/imx6q-marsboard.dts
View File

@@ -100,7 +100,7 @@
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
m25p80@0 {
flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;

32
arch/arm/dts/imx6q-mba6.dtsi
View File

@@ -1,6 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5_mba6x>;
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
&ethphy {
rxdv-skew-ps = <180>;
@@ -16,3 +26,19 @@
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};
&sata {
status = "okay";
};
&iomuxc {
pinctrl_ecspi5_mba6x: ecspi5grp-mba6x {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099
MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099
MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */
>;
};
};

14
arch/arm/dts/imx6q-mba6a.dts
View File

@@ -1,10 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
@@ -12,5 +15,6 @@
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,mba6a", "fsl,imx6q";
compatible = "tq,imx6q-mba6x-a", "tq,mba6a",
"tq,imx6q-tqma6q-a", "fsl,imx6q";
};

14
arch/arm/dts/imx6q-mba6b.dts
View File

@@ -1,10 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
@@ -12,5 +15,6 @@
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,mba6b", "fsl,imx6q";
compatible = "tq,imx6q-mba6x-b", "tq,mba6b",
"tq,imx6q-tqma6q-b", "fsl,imx6q";
};

217
arch/arm/dts/imx6q-mccmon6.dts
View File

@@ -1,39 +1,89 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2019
* Copyright 2016-2017
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Liebherr Nenzig (LWN) iMX6Q";
compatible = "lwn,imx6-mccmon6", "fsl,imx6";
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
spi0 = &ecspi3;
};
chosen {
stdout-path = &uart1;
};
model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
compatible = "lwn,mccmon6", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
backlight_lvds: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100 101 102 103 104 105 106 107 108 109
110 111 112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127 128 129
130 131 132 133 134 135 136 137 138 139
140 141 142 143 144 145 146 147 148 149
150 151 152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167 168 169
170 171 172 173 174 175 176 177 178 179
180 181 182 183 184 185 186 187 188 189
190 191 192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207 208 209
210 211 212 213 214 215 216 217 218 219
220 221 222 223 224 225 226 227 228 229
230 231 232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247 248 249
250 251 252 253 254 255>;
default-brightness-level = <50>;
enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
reg_lvds: regulator-lvds {
compatible = "regulator-fixed";
regulator-name = "lvds_ppen";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_lvds>;
gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
panel-lvds0 {
compatible = "innolux,g121x1-l03";
backlight = <&backlight_lvds>;
power-supply = <&reg_lvds>;
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
spi-max-frequency = <25000000>;
status = "okay";
s25sl032p: flash@0 {
@@ -50,21 +100,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <1>;
/* KSZ9031 PHY SKEW setup - old values * 60 ps */
rxc-skew-ps = <1860>;
txc-skew-ps = <1860>;
txen-skew-ps = <900>;
rxdv-skew-ps = <900>;
rxd0-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd3-skew-ps = <180>;
txd0-skew-ps = <120>;
txd1-skew-ps = <300>;
txd2-skew-ps = <0>;
txd3-skew-ps = <120>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
@@ -181,6 +218,59 @@
};
};
&ldb {
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
non-removable;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
@@ -201,7 +291,13 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_backlight: dispgrp {
fsl,pins = <
/* BLEN_OUT */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
@@ -246,13 +342,6 @@
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
@@ -267,6 +356,19 @@
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>;
};
pinctrl_reg_lvds: reqlvdsgrp {
fsl,pins = <
/* LVDS_PPEN_OUT */
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
@@ -274,6 +376,15 @@
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
@@ -356,27 +467,3 @@
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};

12
arch/arm/dts/imx6q-nitrogen6x.dts
View File

@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013-2019 Boundary Devices, Inc.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2013 Boundary Devices, Inc.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-nitrogen6x.dtsi"

42
arch/arm/dts/imx6q-novena.dts
View File

@@ -61,11 +61,6 @@
reg = <0x10000000 0>;
};
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
};
chosen {
stdout-path = &uart2;
};
@@ -112,7 +107,7 @@
};
panel: panel {
compatible = "innolux,n133hse-ea1", "simple-panel";
compatible = "innolux,n133hse-ea1";
backlight = <&backlight>;
};
@@ -227,20 +222,30 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_novena>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
txen-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <3000>;
txd1-skew-ps = <3000>;
txd2-skew-ps = <3000>;
txd3-skew-ps = <3000>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy {
compatible = "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
txen-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <3000>;
txd1-skew-ps = <3000>;
txd2-skew-ps = <3000>;
txd3-skew-ps = <3000>;
};
};
};
&hdmi {
@@ -460,6 +465,7 @@
};
&pwm1 {
#pwm-cells = <2>;
status = "okay";
};

3
arch/arm/dts/imx6q-phytec-mira-rdk-nand.dts
View File

@@ -8,6 +8,9 @@
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";

7
arch/arm/dts/imx6q-pinfunc.h
View File

@@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6Q_PINFUNC_H
@@ -551,6 +547,7 @@
#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0
#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0

6
arch/arm/dts/imx6q-sabrelite.dts
View File

@@ -5,7 +5,6 @@
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-sabrelite.dtsi"
@@ -17,3 +16,8 @@
&sata {
status = "okay";
};
&ipu1_csi1_from_mipi_vc1 {
clock-lanes = <0>;
data-lanes = <1 2>;
};

9
arch/arm/dts/imx6q-tbs2910.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2014-2019 Soeren Moch <smoch@web.de>
// Copyright 2014 Soeren Moch <smoch@web.de>
/dts-v1/;
@@ -20,7 +20,7 @@
mmc0 = &usdhc2;
mmc1 = &usdhc3;
mmc2 = &usdhc4;
usb0 = &usbotg;
/delete-property/ mmc3;
};
memory@10000000 {
@@ -106,7 +106,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
status = "okay";
@@ -117,6 +116,8 @@
phy: ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
@@ -158,7 +159,7 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
rtc: ds1307@68 {
rtc: rtc@68 {
compatible = "dallas,ds1307";
reg = <0x68>;
};

12
arch/arm/dts/imx6q-tqma6a.dtsi
View File

@@ -1,14 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6q.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};

11
arch/arm/dts/imx6q-tqma6b.dtsi
View File

@@ -1,14 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*/
#include "imx6q.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};

44
arch/arm/dts/imx6q.dtsi
View File

@@ -9,7 +9,6 @@
/ {
aliases {
ipu1 = &ipu2;
video1 = &ipu2;
spi4 = &ecspi5;
};
@@ -50,6 +49,8 @@
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
cpu1: cpu@1 {
@@ -74,6 +75,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -108,6 +110,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -142,6 +145,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -155,14 +159,14 @@
};
};
soc {
soc: soc {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
bus@2000000 { /* AIPS1 */
aips1: bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
@@ -173,15 +177,11 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
};
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6q-iomuxc";
};
};
sata: sata@2200000 {
@@ -406,21 +406,27 @@
&hdmi {
compatible = "fsl,imx6q-hdmi";
port@2 {
reg = <2>;
ports {
port@2 {
reg = <2>;
hdmi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_hdmi>;
hdmi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_hdmi>;
};
};
port@3 {
reg = <3>;
hdmi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_hdmi>;
};
};
};
};
port@3 {
reg = <3>;
hdmi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_hdmi>;
};
};
&iomuxc {
compatible = "fsl,imx6q-iomuxc";
};
&ipu1_csi1 {

5
arch/arm/dts/imx6qdl-cubox-i.dtsi
View File

@@ -55,12 +55,12 @@
pinctrl-0 = <&pinctrl_cubox_i_ir>;
};
pwmleds {
led-controller {
compatible = "pwm-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
front {
led-1 {
active-low;
label = "imx6:red:front";
max-brightness = <248>;
@@ -233,6 +233,7 @@
};
&pwm1 {
#pwm-cells = <2>;
status = "okay";
};

6
arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
View File

@@ -5,9 +5,9 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
@@ -263,6 +263,10 @@
status = "okay";
};
&usbh1 {
disable-over-current;
};
&usdhc2 { /* SD card */
status = "okay";
};

8
arch/arm/dts/imx6qdl-dhcom-som.dtsi
View File

@@ -132,14 +132,15 @@
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
smsc,disable-energy-detect; /* Make plugin detection reliable */
};
@@ -728,6 +729,7 @@
pinctrl_usbh1: usbh1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1
>;
};

7
arch/arm/dts/imx6qdl-gw51xx.dtsi
View File

@@ -13,8 +13,8 @@
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -129,8 +129,6 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -452,7 +450,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};

10
arch/arm/dts/imx6qdl-gw52xx.dtsi
View File

@@ -13,11 +13,10 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -33,8 +32,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -195,8 +192,6 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -547,7 +542,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};

22
arch/arm/dts/imx6qdl-gw53xx.dtsi
View File

@@ -13,11 +13,10 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -33,8 +32,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -137,8 +134,7 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@@ -189,8 +185,6 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -545,14 +539,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -602,7 +593,6 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
@@ -723,12 +713,6 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059

22
arch/arm/dts/imx6qdl-gw54xx.dtsi
View File

@@ -14,11 +14,10 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -34,8 +33,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -146,8 +143,7 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@3 {
@@ -226,8 +222,6 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -615,14 +609,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -680,7 +671,6 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
@@ -818,12 +808,6 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059

7
arch/arm/dts/imx6qdl-gw551x.dtsi
View File

@@ -57,8 +57,8 @@
led0 = &led0;
nand = &gpmi;
ssi0 = &ssi1;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -67,8 +67,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -536,7 +534,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};

29
arch/arm/dts/imx6qdl-gw552x.dtsi
View File

@@ -14,8 +14,8 @@
led1 = &led1;
led2 = &led2;
nand = &gpmi;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -24,8 +24,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -120,15 +118,7 @@
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_h1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
@@ -399,13 +389,9 @@
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
status = "okay"; };
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -414,7 +400,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
@@ -520,12 +505,6 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059

5
arch/arm/dts/imx6qdl-gw553x.dtsi
View File

@@ -55,8 +55,8 @@
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -509,7 +509,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};

14
arch/arm/dts/imx6qdl-gw560x.dtsi
View File

@@ -55,11 +55,9 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc2;
mmc1 = &usdhc3;
ssi0 = &ssi1;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -93,8 +91,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -221,8 +217,7 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@@ -280,8 +275,6 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -661,7 +654,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};

6
arch/arm/dts/imx6qdl-gw5903.dtsi
View File

@@ -75,8 +75,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -223,9 +221,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -534,7 +529,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};

27
arch/arm/dts/imx6qdl-gw5904.dtsi
View File

@@ -55,9 +55,8 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -73,8 +72,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -176,8 +173,7 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@@ -201,9 +197,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
fixed-link {
@@ -474,6 +467,11 @@
};
};
crypto@60 {
compatible = "atmel,atecc508a";
reg = <0x60>;
};
imu@6a {
compatible = "st,lsm9ds1-imu";
reg = <0x6a>;
@@ -588,14 +586,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
@@ -756,12 +751,6 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059

9
arch/arm/dts/imx6qdl-gw5907.dtsi
View File

@@ -13,8 +13,8 @@
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -23,8 +23,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -131,8 +129,6 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -380,7 +376,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};

7
arch/arm/dts/imx6qdl-gw5910.dtsi
View File

@@ -13,7 +13,6 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
};
chosen {
@@ -27,8 +26,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -146,9 +143,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -402,7 +396,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};

22
arch/arm/dts/imx6qdl-gw5912.dtsi
View File

@@ -13,10 +13,9 @@
led0 = &led0;
led1 = &led1;
led2 = &led2;
mmc0 = &usdhc3;
nand = &gpmi;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -25,8 +24,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -120,8 +117,7 @@
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
@@ -142,9 +138,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -381,8 +374,6 @@
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@@ -432,7 +423,6 @@
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};
@@ -563,12 +553,6 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059

10
arch/arm/dts/imx6qdl-gw5913.dtsi
View File

@@ -13,8 +13,8 @@
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbotg;
usb1 = &usbh1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
@@ -23,8 +23,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@@ -121,9 +119,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <300>;
status = "okay";
};
@@ -346,7 +341,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "host";
status = "okay";
};

2
arch/arm/dts/imx6qdl-hummingboard2.dtsi
View File

@@ -203,7 +203,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>;
cs-gpios = <&gpio2 26 0>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
status = "okay";
};

19
arch/arm/dts/imx6qdl-icore.dtsi
View File

@@ -150,10 +150,23 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
phy-mode = "rmii";
phy-handle = <&eth_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
reset-assert-us = <4000>;
reset-deassert-us = <4000>;
};
};
};
&gpmi {
@@ -232,6 +245,7 @@
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
@@ -384,7 +398,7 @@
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
@@ -396,6 +410,7 @@
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
>;
};

608
arch/arm/dts/imx6qdl-mba6.dtsi
View File

@@ -1,48 +1,177 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
/delete-property/ mmc2;
/delete-property/ mmc3;
rtc0 = &rtc0;
};
chosen {
linux,stdout-path = &uart2;
stdout-path = &uart2;
};
regulators {
reg_mba6_3p3v: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "supply-mba6-3p3v";
reg = <1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
beeper: gpio-beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiobeeper>;
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
};
gpio_buttons: gpio-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiobuttons>;
button1 {
label = "s6";
linux,code = <KEY_F6>;
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
wakeup-source;
};
reg_otgvbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_otgpwr>;
regulator-name = "otg-vbus-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin_supply = <&reg_3p3v>;
button2 {
label = "s7";
linux,code = <KEY_F7>;
gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button3 {
label = "s8";
linux,code = <KEY_F8>;
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioled>;
led1 {
label = "led1";
gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led2 {
label = "led2";
gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_mba6_3p3v: regulator-mba6-3p3v {
compatible = "regulator-fixed";
regulator-name = "supply-mba6-3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regpcie>;
regulator-name = "supply-pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/* PCIE.PWR_EN */
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_mba6_3p3v>;
};
reg_vcc3v3_audio: regulator-vcc3v3-audio {
compatible = "regulator-fixed";
regulator-name = "vcc3v3-audio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_mba6_3p3v>;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
model = "imx-audio-tlv320aic32x4";
ssi-controller = <&ssi1>;
audio-codec = <&tlv320aic32x4>;
audio-asrc = <&asrc>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
mux-int-port = <1>;
mux-ext-port = <3>;
};
};
&audmux {
status = "okay";
ssi0 {
fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
>;
};
aud3 {
fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
};
&fec {
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <100>;
phy-handle = <&ethphy>;
mac-address = [00 00 00 00 00 00];
status = "okay";
mdio {
@@ -50,134 +179,95 @@
#size-cells = <0>;
ethphy: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
force-master;
max-speed = <1000>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <100000>;
micrel,force-master;
max-speed = <1000>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
mba6 {
pinctrl_enet: enetgrp {
fsl,pins = <
/* FEC phy IRQ */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
/* FEC phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
/* DSE = 100, 100k up, SPEED = MED */
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
/* DSE = 111, pull 100k up */
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
/* DSE = 111, pull external */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */
/* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
>;
};
pinctrl_reg_otgpwr: regotgpwrgrp {
fsl,pins = <
/* OTG_PWR */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
>;
};
&i2c1 {
tlv320aic32x4: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec>;
ldoin-supply = <&reg_vcc3v3_audio>;
iov-supply = <&reg_mba6_3p3v>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
uart-has-rtscts;
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay";
@@ -186,22 +276,260 @@
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
power-active-high;
over-current-active-low;
srp-disable;
hnp-disable;
adp-disable;
dr_mode = "otg";
vbus-supply = <&reg_otgvbus>;
status = "okay";
};
&usdhc2 { /* Baseboard Slot */
/* SD card slot */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_mba6_3p3v>;
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
/* does not work on unmodified starter kit */
/* fsl,ext-reset-output; */
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
>;
};
pinctrl_codec: codecgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
>;
};
pinctrl_ecspi1_mba6: ecspimba6grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
/* FEC phy IRQ */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
/* FEC phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
/* DSE = 100, 100k up, SPEED = MED */
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
/* DSE = 111, pull 100k up */
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
/* DSE = 111, pull external */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
>;
};
pinctrl_gpiobeeper: gpiobeepergrp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
>;
};
pinctrl_gpiobuttons: gpiobuttongrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
>;
};
pinctrl_gpioled: gpioledgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
/* 100 k PD, DSE 120 OHM, SPPEED LO */
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
/* 100 k PD, DSE 120 OHM, SPPEED LO */
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
/* 100 k PD, DSE 120 OHM, SPPEED LO */
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
>;
};
pinctrl_regpcie: regpciegrp {
fsl,pins = <
/* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
>;
};
pinctrl_wdog1: wdog1grp {
fsl,pins = <
/* Watchdog out */
MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
>;
};
};

35
arch/arm/dts/imx6qdl-mba6a.dtsi
View File

@@ -1,39 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c1 {
sensor1: lm75@49 {
compatible = "lm75";
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
};
eeprom1: m24c64@57 {
compatible = "st,24c64", "at24";
m24c64_57: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
};
rtc1: ds1339@68 {
compatible = "ds1339";
rtc0: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&iomuxc {
mba6 {
pinctrl_enet_fix: enetfixgrp {
fsl,pins = <
/* ENET ping patch */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
};

40
arch/arm/dts/imx6qdl-mba6b.dtsi
View File

@@ -1,6 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
&fec {
pinctrl-names = "default";
@@ -9,37 +13,37 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_recovery>;
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
sensor1: lm75@49 {
compatible = "lm75";
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
};
eeprom1: m24c64@57 {
compatible = "st,24c64", "at24";
m24c64_57: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
};
rtc1: ds1339@68 {
compatible = "ds1339";
rtc0: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&iomuxc {
mba6 {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
};

731
arch/arm/dts/imx6qdl-nitrogen6x.dtsi
View File

@@ -1,69 +1,692 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013-2019 Boundary Devices, Inc.
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2013 Boundary Devices, Inc.
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6qdl-sabrelite.dtsi"
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
#undef GP_ENET_PHY_RESET
#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW>
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW>
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
>;
/ {
chosen {
stdout-path = &uart2;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* Spare */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
>;
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>;
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
reg_can_xcvr: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
reg_wlan_vmmc: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan_vmmc>;
regulator-name = "reg_wlan_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
reg_usb_h1_vbus: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-nitrogen6x-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
lcd_display: disp0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_j15>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0xc0000>;
};
partition@c0000 {
label = "env";
reg = <0xc0000 0x2000>;
};
partition@c2000 {
label = "splash";
reg = <0xc2000 0x13e000>;
};
};
};
&fec {
#if 0
phy-reset-gpios = GP_ENET_PHY_RESET;
#endif
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy {
compatible = "ethernet-phy-ieee802.3-c22";
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
};
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&usdhc3 {
/delete-property/ wp-gpios;
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
rtc: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-nitrogen6x {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_can_xcvr: can-xcvrgrp {
fsl,pins = <
/* Flexcan XCVR enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_j15: j15grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
>;
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&ldb {
status = "okay";
lvds-channel@0 {
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&pcie {
status = "okay";
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
non-removable;
vmmc-supply = <&reg_wlan_vmmc>;
cap-power-off-card;
keep-power-in-suspend;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
ref-clock-frequency = <38400000>;
};
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};

119
arch/arm/dts/imx6qdl-phytec-mira-peb-av-02.dtsi Normal file
View File

@@ -0,0 +1,119 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik
* Author: Christian Hemp <c.hemp@phytec.de>
*/
/ {
display: display0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0>;
interface-pix-fmt = "rgb24";
status = "disabled";
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
display0_out: endpoint {
remote-endpoint = <&peb_panel_lcd_in>;
};
};
};
panel-lcd {
compatible = "edt,etm0700g0edh6";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_pwr>;
power-supply = <&reg_display>;
enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
status = "disabled";
port {
peb_panel_lcd_in: endpoint {
remote-endpoint = <&display0_out>;
};
};
};
reg_display: regulator-peb-display {
compatible = "regulator-fixed";
regulator-name = "peb-display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&i2c1 {
edt_ft5x06: touchscreen@38 {
compatible = "edt,edt-ft5406";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;
reg = <0x38>;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_NONE>;
status = "disabled";
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&iomuxc {
pinctrl_disp0: disp0grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_disp0_pwr: disp0pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
>;
};
pinctrl_edt_ft5x06: edtft5x06grp {
fsl,pins = <
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1
>;
};
};

71
arch/arm/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi Normal file
View File

@@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik
* Author: Christian Hemp <c.hemp@phytec.de>
*/
#include <dt-bindings/input/input.h>
/ {
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
status = "disabled";
power {
label = "Power Button";
gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
sleep {
label = "Sleep Button";
gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_SLEEP>;
};
};
user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_leds>;
status = "disabled";
user-led1 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
user-led2 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
user-led3 {
gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
};
};
&iomuxc {
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0
>;
};
pinctrl_user_leds: userledsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
>;
};
};

85
arch/arm/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi Normal file
View File

@@ -0,0 +1,85 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Yunus Bas <y.bas@phytec.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_wl_en: regulator-wl-en {
compatible = "regulator-fixed";
regulator-name = "wlan_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wl>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
status = "disabled";
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_bt>;
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_wl>;
vmmc-supply = <&reg_wl_en>;
bus-width = <4>;
non-removable;
no-1-8-v;
status = "disabled";
brmcf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl_uart3_bt: uart3grp-bt {
fsl,pins = <
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */
>;
};
pinctrl_usdhc3_wl: usdhc3grp-wl {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_wl: wlgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */
>;
};
};

32
arch/arm/dts/imx6qdl-phytec-mira.dtsi
View File

@@ -145,8 +145,11 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "disabled";
@@ -185,8 +188,11 @@
};
&i2c2 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "disabled";
};
@@ -218,6 +224,7 @@
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -255,6 +262,7 @@
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
no-1-8-v;
disable-wp;
status = "disabled";
};
@@ -298,6 +306,20 @@
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
@@ -305,10 +327,10 @@
>;
};
pinctrl_i2c1: i2c1grp {
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
>;
};

30
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
View File

@@ -78,17 +78,21 @@
};
&i2c3 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
compatible = "st,24c32", "atmel,24c32";
pagesize = <32>;
reg = <0x50>;
};
pmic@58 {
pmic: pmic@58 {
compatible = "dlg,da9062";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
@@ -96,6 +100,8 @@
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
da9062_rtc: rtc {
compatible = "dlg,da9062-rtc";
@@ -107,6 +113,17 @@
watchdog {
compatible = "dlg,da9062-watchdog";
dlg,use-sw-pm;
};
thermal {
compatible = "dlg,da9062-thermal";
status = "disabled";
};
gpio {
compatible = "dlg,da9062-gpio";
status = "disabled";
};
regulators {
@@ -255,6 +272,13 @@
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1

226
arch/arm/dts/imx6qdl-pico.dtsi
View File

@@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
@@ -9,11 +9,6 @@
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg;
};
chosen {
stdout-path = &uart1;
};
@@ -42,6 +37,22 @@
regulator-always-on;
};
reg_1p5v: regulator-1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_2p8v: regulator-2p8v {
compatible = "regulator-fixed";
regulator-name = "2P8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_vbus>;
@@ -51,6 +62,81 @@
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
};
codec_osc: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6-pico-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 50000 0>;
brightness-levels = <0 36 72 108 144 180 216 255>;
default-brightness-level = <6>;
status = "okay";
};
reg_lcd_3v3: regulator-lcd-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_lcd>;
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
lcd_display: disp0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel {
compatible = "vxt,vl050-8048nt-c01";
backlight = <&backlight>;
power-supply = <&reg_lcd_3v3>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
};
&audmux {
@@ -81,7 +167,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -90,7 +176,18 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@1 {
reg = <1>;
qca,clk-out-frequency = <125000000>;
};
};
};
&hdmi {
@@ -102,6 +199,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
sgtl5000: audio-codec@a {
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&codec_osc>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_1p8v>;
};
};
&i2c2 {
@@ -109,6 +215,40 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
interrupt-parent = <&gpio5>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
wakeup-source;
};
camera@3c {
compatible = "ovti,ov5645";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5645>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&reg_1p8v>;
vdda-supply = <&reg_2p8v>;
vddd-supply = <&reg_1p5v>;
enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
port {
ov5645_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&i2c3 {
@@ -117,11 +257,28 @@
status = "okay";
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5645_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reset>;
reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
@@ -161,14 +318,14 @@
&uart2 { /* Bluetooth module */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
uart-has-rtscts;
status = "okay";
};
@@ -219,7 +376,6 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x4001b0b5 /* PICO_P25 */
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */
@@ -316,6 +472,48 @@
>;
};
pinctrl_ipu1: ipu1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ov5645: ov5645grp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
>;
};
pinctrl_pcie_reset: pciegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0
@@ -346,6 +544,12 @@
>;
};
pinctrl_reg_lcd: reglcdgrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1

117
arch/arm/dts/imx6qdl-sabreauto.dtsi
View File

@@ -12,6 +12,7 @@
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
@@ -75,39 +76,49 @@
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_audio: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
regulator-name = "can-en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can_stby: regulator-can-stby {
compatible = "regulator-fixed";
regulator-name = "can-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can_en>;
};
sound-cs42888 {
@@ -219,6 +230,8 @@
accelerometer@1c {
compatible = "fsl,mma8451";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mma8451_int>;
interrupt-parent = <&gpio6>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
};
@@ -254,12 +267,12 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
flash: m25p80@0 {
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
@@ -285,6 +298,21 @@
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
fsl,magic-packet;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can_stby>;
status = "disabled"; /* pin conflict with fec */
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
@@ -503,6 +531,20 @@
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
@@ -589,6 +631,12 @@
>;
};
pinctrl_mma8451_int: mma8451intgrp {
fsl,pins = <
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
@@ -753,11 +801,16 @@
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pcie {
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;

876
arch/arm/dts/imx6qdl-sabrelite.dtsi
View File

@@ -8,336 +8,683 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1
#define GP_ECSPI1_NOR_CS <&gpio3 19 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
#undef GP_ENET_PHY_RESET
#define GP_ENET_PHY_RESET <&gpio3 23 GPIO_ACTIVE_LOW>
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x030b0
#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW>
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* Spare */
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_1: i2c1-1grp {
fsl,pins = <
#define GP_I2C1_SCL <&gpio3 21 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
#define GP_I2C1_SDA <&gpio3 28 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c2_1: i2c2-1grp {
fsl,pins = <
#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_i2c3_1: i2c3-1grp {
fsl,pins = <
#define GP_I2C3_SCL <&gpio1 5 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
#define GP_I2C3_SDA <&gpio7 11 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
fsl,pins = <
#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW>
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW>
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_HIGH>
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
#define GP_USDHC4_CD <&gpio2 6 GPIO_ACTIVE_LOW>
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
>;
};
};
/ {
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc4;
pwm_lcd = &pwm1;
pwm_lvds = &pwm4;
};
chosen {
stdout-path = &uart2;
};
memory {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
reg_3p3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
reg_can_xcvr: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
reg_1p5v: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_1p8v: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_2p8v: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "2P8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = GP_REG_USBOTG;
enable-active-high;
mipi_xclk: mipi_xclk {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <22000000>;
clock-output-names = "mipi_pwm3";
pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
lcd_display: disp0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_j15>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
data-shift = <12>; /* Lines 19:12 used */
hsync-active = <1>;
vync-active = <1>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi1 {
cs-gpios = GP_ECSPI1_NOR_CS;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mtd@00000000 {
label = "U-Boot";
reg = <0x0 0xC0000>;
};
mtd@000C0000 {
label = "env";
reg = <0xC0000 0x2000>;
};
mtd@000C2000 {
label = "splash";
reg = <0xC2000 0x13e000>;
};
};
};
&fec {
phy-handle = <&ethphy>;
phy-mode = "rgmii";
#if 0
phy-reset-gpios = GP_ENET_PHY_RESET;
#endif
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
rxdv-skew-ps = <0>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
status = "okay";
txc-skew-ps = <3000>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
mdio {
#address-cells = <0>;
#size-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy {
interrupts-extended = GPIRQ_ENET_PHY;
compatible = "ethernet-phy-ieee802.3-c22";
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_1>;
scl-gpios = GP_I2C1_SCL;
sda-gpios = GP_I2C1_SDA;
status = "okay";
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_1>;
scl-gpios = GP_I2C2_SCL;
sda-gpios = GP_I2C2_SDA;
status = "okay";
hdmi_edid: edid@50 {
compatible = "fsl,imx6-hdmi-i2c";
reg = <0x50>;
ov5640: camera@40 {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x40>;
clocks = <&mipi_xclk>;
clock-names = "xclk";
DOVDD-supply = <&reg_1p8v>;
AVDD-supply = <&reg_2p8v>;
DVDD-supply = <&reg_1p5v>;
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
port {
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
ov5642: camera@42 {
compatible = "ovti,ov5642";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5642>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
clock-names = "xclk";
reg = <0x42>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
port {
ov5642_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_1>;
scl-gpios = GP_I2C3_SCL;
sda-gpios = GP_I2C3_SDA;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-sabrelite {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_can_xcvr: can-xcvrgrp {
fsl,pins = <
/* Flexcan XCVR enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
>;
};
pinctrl_j15: j15grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
>;
};
pinctrl_ov5642: ov5642grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&ldb {
status = "okay";
lvds-channel@0 {
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&pcie {
status = "okay";
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -351,10 +698,7 @@
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
disable-over-current;
reset-gpios = GP_USBH1_HUB_RESET;
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
@@ -369,8 +713,8 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = GP_USDHC3_CD;
wp-gpios = GP_USDHC3_WP;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
@@ -378,7 +722,21 @@
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = GP_USDHC4_CD;
cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};

210
arch/arm/dts/imx6qdl-sabresd.dtsi
View File

@@ -8,64 +8,62 @@
#include <dt-bindings/input/input.h>
/ {
aliases {
mmc1 = &usdhc3;
};
chosen {
stdout-path = &uart1;
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 29 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_audio: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 0>;
enable-active-high;
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pcie: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 19 0>;
enable-active-high;
};
reg_sensors: regulator-sensors {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sensors_reg>;
regulator-name = "sensors-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
gpio-keys {
@@ -99,17 +97,24 @@
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-asrc = <&asrc>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
"IN3R", "AMIC",
"DMIC", "MICBIAS",
"DMICDAT", "DMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
backlight_lvds: backlight-lvds {
@@ -187,12 +192,12 @@
};
&ecspi1 {
cs-gpios = <&gpio4 9 0>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
@@ -205,8 +210,21 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@1 {
reg = <1>;
qca,clk-out-frequency = <125000000>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
&hdmi {
@@ -244,6 +262,17 @@
>;
};
accelerometer@1c {
compatible = "fsl,mma8451";
reg = <0x1c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
interrupt-parent = <&gpio1>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&reg_sensors>;
vddio-supply = <&reg_sensors>;
};
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
@@ -276,6 +305,16 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
interrupt-parent = <&gpio6>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
};
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
@@ -414,6 +453,27 @@
interrupts = <7 2>;
wakeup-gpios = <&gpio6 7 0>;
};
magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_RISING>;
vdd-supply = <&reg_sensors>;
vddio-supply = <&reg_sensors>;
};
light-sensor@44 {
compatible = "isil,isl29023";
reg = <0x44>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
interrupt-parent = <&gpio3>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&reg_sensors>;
};
};
&iomuxc {
@@ -488,6 +548,13 @@
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
@@ -495,6 +562,12 @@
>;
};
pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -502,6 +575,12 @@
>;
};
pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -509,6 +588,18 @@
>;
};
pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
fsl,pins = <
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1
>;
};
pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
@@ -557,6 +648,12 @@
>;
};
pinctrl_sensors_reg: sensorsreggrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
@@ -658,6 +755,7 @@
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -675,10 +773,22 @@
vin-supply = <&sw1c_reg>;
};
&reg_vdd1p1 {
vin-supply = <&vgen5_reg>;
};
&reg_vdd2p5 {
vin-supply = <&vgen5_reg>;
};
&snvs_poweroff {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&ssi2 {
status = "okay";
};

1
arch/arm/dts/imx6qdl-sr-som-ti.dtsi
View File

@@ -153,6 +153,7 @@
bus-width = <4>;
keep-power-in-suspend;
mmc-pwrseq = <&pwrseq_ti_wifi>;
cap-power-off-card;
non-removable;
vmmc-supply = <&vcc_3v3>;
/* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */

31
arch/arm/dts/imx6qdl-sr-som.dtsi
View File

@@ -53,7 +53,6 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
/*
@@ -69,16 +68,30 @@
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
/*
* The PHY can appear either:
* - AR8035: at address 0 or 4
* - ADIN1300: at address 1
* Actual address being detected at runtime.
*/
reg = <0xffffffff>;
/*
* The PHY can appear at either address 0 or 4 due to the
* configuration (LED) pin not being pulled sufficiently.
*/
ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <125000000>;
qca,smarteee-tw-us-1g = <24>;
};
ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
qca,smarteee-tw-us-1g = <24>;
};
/*
* ADIN1300 (som rev 1.9 or later) is always at address 1. It
* will be enabled automatically by U-Boot if detected.
*/
ethernet-phy@1 {
reg = <1>;
adi,phy-output-clock = "125mhz-free-running";
status = "disabled";
};
};
};

328
arch/arm/dts/imx6qdl-tqma6.dtsi
View File

@@ -1,40 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
mmc0 = &usdhc3;
/delete-property/ mmc1;
/delete-property/ mmc2;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
reg = <0>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
flash: m25p80@0 {
status = "okay";
compatible = "micron,n25q128a13", "n25q128a13";
m25p80: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
#address-cells = <1>;
@@ -44,151 +34,163 @@
};
&iomuxc {
tqma6 {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
};
pinctrl_i2c1_tqma6: i2c1-tqma6grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c3_tqma6: i2c3-tqma6grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
};
pinctrl_i2c1_recovery: i2c1recoverygrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899
MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
&pmic {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio6>;
interrupts = <10 8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
regulators {
reg_vddcore: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v_600mA: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-always-on;
};
reg_snvs_3v: vsnvs {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
reg_vrefddr: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
/* not used */
};
reg_vgen2_1v2_eth: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen4_1v8: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_1v8_eth: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulators {
reg_vddcore: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v_600mA: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-always-on;
};
reg_snvs_3v: vsnvs {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
reg_vrefddr: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
/* not used */
};
reg_vgen2_1v2_eth: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen4_1v8: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_1v8_eth: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* eMMC */
@@ -198,6 +200,8 @@
vmmc-supply = <&reg_3p3v>;
non-removable;
disable-wp;
no-sd;
no-sdio;
bus-width = <8>;
#address-cells = <1>;
#size-cells = <0>;

46
arch/arm/dts/imx6qdl-tqma6a.dtsi
View File

@@ -1,27 +1,53 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
&fec {
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_tqma6>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_recovery>;
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
pmic: pf0100@08 {
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor0: lm75@48 {
compatible = "lm75";
sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
eeprom0: m24c64@50 {
compatible = "st,24c64", "at24";
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};
&iomuxc {
/*
* This pinmuxing is required for the ERR006687 workaround. Board
* DTS files that enable the FEC controller with
* fsl,err006687-workaround-present must include this group.
*/
pinctrl_enet_fix: enetfixgrp {
fsl,pins = <
/* ENET ping patch */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};

28
arch/arm/dts/imx6qdl-tqma6b.dtsi
View File

@@ -1,27 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_tqma6>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
pmic: pf0100@08 {
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor0: lm75@48 {
compatible = "lm75";
sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
eeprom0: m24c64@50 {
compatible = "st,24c64", "at24";
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};

4
arch/arm/dts/imx6qdl-udoo.dtsi
View File

@@ -4,7 +4,9 @@
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
backlight = &backlight;
@@ -293,7 +295,7 @@
pinctrl-0 = <&pinctrl_usbh>;
vbus-supply = <&reg_usb_h1_vbus>;
clocks = <&clks IMX6QDL_CLK_CKO>;
status = "okay";
status = "disabled";
};
&usbotg {

2
arch/arm/dts/imx6qdl-wandboard-revd1.dtsi
View File

@@ -142,7 +142,6 @@
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
@@ -166,7 +165,6 @@
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};

102
arch/arm/dts/imx6qdl-wandboard.dtsi
View File

@@ -8,10 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
mmc0 = &usdhc3;
};
chosen {
stdout-path = &uart1;
};
@@ -37,6 +33,30 @@
spdif-out;
};
reg_1p5v: regulator-1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_2p8v: regulator-2p8v {
compatible = "regulator-fixed";
regulator-name = "2P8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
@@ -77,15 +97,21 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
codec: sgtl5000@a {
@@ -98,6 +124,29 @@
VDDIO-supply = <&reg_3p3v>;
lrclk-strength = <3>;
};
camera@3c {
compatible = "ovti,ov5645";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5645>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&reg_1p8v>;
vdda-supply = <&reg_2p8v>;
vddd-supply = <&reg_1p5v>;
enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
port {
ov5645_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&iomuxc {
@@ -132,7 +181,6 @@
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@@ -143,6 +191,13 @@
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -150,12 +205,27 @@
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0
>;
};
pinctrl_mclk: mclkgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_ov5645: ov5645grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
@@ -231,9 +301,6 @@
phy-mode = "rgmii-id";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
mdio {
@@ -242,6 +309,21 @@
ethphy: ethernet-phy@1 {
reg = <1>;
qca,clk-out-frequency = <125000000>;
};
};
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5645_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};

194
arch/arm/dts/imx6qdl.dtsi
View File

@@ -4,6 +4,7 @@
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -13,10 +14,8 @@
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
@@ -46,39 +45,34 @@
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usb0 = &usbotg;
usb1 = &usbh1;
usb2 = &usbh2;
usb3 = &usbh3;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
ldb: ldb {
#address-cells = <1>;
#size-cells = <0>;
@@ -139,6 +133,16 @@
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -159,10 +163,8 @@
clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
};
gpmi: gpmi-nand@112000 {
gpmi: nand-controller@112000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -180,8 +182,6 @@
};
hdmi: hdmi@120000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00120000 0x9000>;
interrupts = <0 115 0x04>;
gpr = <&gpr>;
@@ -190,19 +190,24 @@
clock-names = "iahb", "isfr";
status = "disabled";
port@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_hdmi>;
port@0 {
reg = <0>;
hdmi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_hdmi>;
};
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
hdmi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_hdmi>;
hdmi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_hdmi>;
};
};
};
};
@@ -216,6 +221,7 @@
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&pd_pu>;
#cooling-cells = <2>;
};
gpu_2d: gpu@134000 {
@@ -226,6 +232,7 @@
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&pd_pu>;
#cooling-cells = <2>;
};
timer@a00600 {
@@ -245,7 +252,7 @@
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -257,7 +264,7 @@
};
pcie: pcie@1ffc000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
compatible = "fsl,imx6q-pcie";
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
@@ -265,8 +272,8 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
<0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -326,7 +333,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
<&clks IMX6QDL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -340,7 +347,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
<&clks IMX6QDL_CLK_ECSPI2>;
clock-names = "ipg", "per";
dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -354,7 +361,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
<&clks IMX6QDL_CLK_ECSPI3>;
clock-names = "ipg", "per";
dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -368,7 +375,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
<&clks IMX6QDL_CLK_ECSPI4>;
clock-names = "ipg", "per";
dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -474,7 +481,7 @@
status = "okay";
};
spba@203c000 {
spba-bus@203c000 {
reg = <0x0203c000 0x4000>;
};
};
@@ -498,7 +505,7 @@
};
pwm1: pwm@2080000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -509,7 +516,7 @@
};
pwm2: pwm@2084000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -520,7 +527,7 @@
};
pwm3: pwm@2088000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -531,7 +538,7 @@
};
pwm4: pwm@208c000 {
#pwm-cells = <2>;
#pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -541,27 +548,29 @@
status = "disabled";
};
can1: flexcan@2090000 {
can1: can@2090000 {
compatible = "fsl,imx6q-flexcan";
reg = <0x02090000 0x4000>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
<&clks IMX6QDL_CLK_CAN1_SERIAL>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x34 28>;
status = "disabled";
};
can2: flexcan@2094000 {
can2: can@2094000 {
compatible = "fsl,imx6q-flexcan";
reg = <0x02094000 0x4000>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
<&clks IMX6QDL_CLK_CAN2_SERIAL>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x34 29>;
status = "disabled";
};
gpt: gpt@2098000 {
gpt: timer@2098000 {
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -648,7 +657,7 @@
#interrupt-cells = <2>;
};
kpp: kpp@20b8000 {
kpp: keypad@20b8000 {
compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -656,22 +665,22 @@
status = "disabled";
};
wdog1: wdog@20bc000 {
wdog1: watchdog@20bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_DUMMY>;
clocks = <&clks IMX6QDL_CLK_IPG>;
};
wdog2: wdog@20c0000 {
wdog2: watchdog@20c0000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_DUMMY>;
clocks = <&clks IMX6QDL_CLK_IPG>;
status = "disabled";
};
clks: ccm@20c4000 {
clks: clock-controller@20c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -680,7 +689,7 @@
};
anatop: anatop@20c8000 {
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -753,7 +762,7 @@
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-enable-ramp-delay = <150>;
regulator-enable-ramp-delay = <380>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
@@ -781,6 +790,17 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupt-parent = <&gpc>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
};
usbphy1: usbphy@20c9000 {
@@ -820,6 +840,15 @@
status = "disabled";
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
compatible = "fsl,imx6q-snvs-lpgpr";
};
@@ -835,7 +864,7 @@
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6q-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,8 +877,7 @@
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&clks IMX6QDL_CLK_IPG>;
clock-names = "ipg";
@@ -886,7 +914,7 @@
};
};
iomuxc: iomuxc@20e0000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x20e0000 0x4000>;
};
@@ -905,7 +933,7 @@
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SDMA>,
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
@@ -913,14 +941,14 @@
};
};
bus@2100000 { /* AIPS2 */
aips2: bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
crypto: caam@2100000 {
crypto: crypto@2100000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@@ -932,13 +960,13 @@
<&clks IMX6QDL_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
sec_jr0: jr0@1000 {
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -981,6 +1009,8 @@
reg = <0x02184400 0x200>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbphy = <&usbphynop1>;
phy_type = "hsic";
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
ahb-burst-config = <0x0>;
@@ -994,6 +1024,8 @@
reg = <0x02184600 0x200>;
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbphy = <&usbphynop2>;
phy_type = "hsic";
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
ahb-burst-config = <0x0>;
@@ -1013,13 +1045,14 @@
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupt-names = "int0", "pps";
interrupts-extended =
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
<0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp";
clock-names = "ipg", "ahb", "ptp", "enet_out";
fsl,stop-mode = <&gpr 0x34 27>;
status = "disabled";
};
@@ -1030,7 +1063,7 @@
<0 126 IRQ_TYPE_LEVEL_HIGH>;
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -1042,7 +1075,7 @@
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -1054,7 +1087,7 @@
status = "disabled";
};
usdhc3: usdhc@2198000 {
usdhc3: mmc@2198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -1066,7 +1099,7 @@
status = "disabled";
};
usdhc4: usdhc@219c000 {
usdhc4: mmc@219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -1112,13 +1145,16 @@
reg = <0x021ac000 0x4000>;
};
mmdc0: mmdc@21b0000 { /* MMDC0 */
mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
mmdc1: mmdc@21b4000 { /* MMDC1 */
mmdc1: memory-controller@21b4000 { /* MMDC1 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
status = "disabled";
};
weim: weim@21b8000 {
@@ -1132,10 +1168,24 @@
status = "disabled";
};
ocotp: ocotp@21bc000 {
ocotp: efuse@21bc000 {
compatible = "fsl,imx6q-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6QDL_CLK_IIM>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
};
tzasc@21d0000 { /* TZASC1 */

14
include/dt-bindings/clock/imx6qdl-clock.h
View File

@@ -1,9 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
@@ -269,6 +266,13 @@
#define IMX6QDL_CLK_PRG0_APB 256
#define IMX6QDL_CLK_PRG1_APB 257
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_END 259
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
#define IMX6QDL_CLK_EPIT1 261
#define IMX6QDL_CLK_EPIT2 262
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_DCIC1 264
#define IMX6QDL_CLK_DCIC2 265
#define IMX6QDL_CLK_END 266
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */