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stm32mp: cleanup cpu.c

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Move all defines at the beginning of the file

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay
2018-03-19 19:09:20 +01:00
committed by Tom Rini
parent c5b0bca4c3
commit cda3dcb670
1 changed files with 21 additions and 23 deletions
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44
arch/arm/mach-stm32mp/cpu.c
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@@ -8,16 +8,16 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/stm32.h> #include <asm/arch/stm32.h>
void enable_caches(void) /* RCC register */
{ #define RCC_TZCR (STM32_RCC_BASE + 0x00)
/* Enable D-cache. I-cache is already enabled in start.S */ #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
dcache_enable(); #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
} #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
#define RCC_BDCR_VSWRST BIT(31)
#define RCC_BDCR_RTCSRC GENMASK(17, 16)
#define RCC_DBGCFGR_DBGCKEN BIT(8)
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* Security register */
/**********************************************
* Security init
*********************************************/
#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
@@ -30,13 +30,11 @@ void enable_caches(void)
#define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_CR1 (STM32_PWR_BASE + 0x00)
#define PWR_CR1_DBP BIT(8) #define PWR_CR1_DBP BIT(8)
#define RCC_TZCR (STM32_RCC_BASE + 0x00) /* DBGMCU register */
#define RCC_BDCR (STM32_RCC_BASE + 0x0140) #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
#define RCC_BDCR_VSWRST BIT(31)
#define RCC_BDCR_RTCSRC GENMASK(17, 16)
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
static void security_init(void) static void security_init(void)
{ {
/* Disable the backup domain write protection */ /* Disable the backup domain write protection */
@@ -93,15 +91,9 @@ static void security_init(void)
writel(0x0, TAMP_CR1); writel(0x0, TAMP_CR1);
} }
/********************************************** /*
* Debug init * Debug init
*********************************************/ */
#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
#define RCC_DBGCFGR_DBGCKEN BIT(8)
#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
static void dbgmcu_init(void) static void dbgmcu_init(void)
{ {
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
@@ -125,6 +117,12 @@ int arch_cpu_init(void)
return 0; return 0;
} }
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#if defined(CONFIG_DISPLAY_CPUINFO) #if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void) int print_cpuinfo(void)
{ {