dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-09-18 09:02:25 +02:00
Code Issues Packages Projects Releases Wiki Activity

sunxi: H6: DRAM: follow recommended PHY init algorithm

Browse Source 
The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.

Follow this recommendation by setting bit 0 in a separate step.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Andre Przywara
2019-07-15 02:27:05 +01:00
committed by Ondrej Jirman
parent 0edd36766a
commit cb9c7bcb92
1 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-sunxi/dram_sun50i_h6.c
View File

@@ -75,12 +75,14 @@ static void mctl_core_init(struct dram_para *para)
mctl_channel_init(para); mctl_channel_init(para);
} }
/* PHY initialisation */
static void mctl_phy_pir_init(u32 val) static void mctl_phy_pir_init(u32 val)
{ {
struct sunxi_mctl_phy_reg * const mctl_phy = struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
writel(val | BIT(0), &mctl_phy->pir); writel(val, &mctl_phy->pir);
writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
} }