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board: ns3: define ddr memory layout

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Add both DRAM banks memory information and
the corresponding MMU page table mappings.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Rayagonda Kokatanur
2020-07-15 22:49:04 +05:30
committed by Tom Rini
parent 3edecba784
commit c8b98482d8
3 changed files with 127 additions and 4 deletions
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23
arch/arm/dts/ns3-board.dts
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@@ -5,6 +5,29 @@
/dts-v1/;
#include <dt-bindings/memory/bcm-ns3-mc.h>
/*
* Single mem reserve region which includes the following:
* Components name Start Addr Size
* ------------------------------------------------
* GIC LPI tables 0x8ad7_0000 0x0009_0000
* Nitro FW 0x8ae0_0000 0x0020_0000
* Nitro Crash dump 0x8b00_0000 0x0200_0000
* OPTEE OS 0x8d00_0000 0x0200_0000
* BL31 services 0x8f00_0000 0x0010_0000
* Tmon 0x8f10_0000 0x0000_1000
* LPM/reserved 0x8f10_1000 0x0000_1000
* ATF to Bl33 info 0x8f10_2000 0x0000_1000
* ATF error logs 0x8f10_3000 0x0001_0000
* Error log parser 0x8f11_3000 0x0010_0000
*/
/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
/* CRMU page tables */
/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
#include "ns3.dtsi"
/ {