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esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros

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For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
This commit is contained in:
Wang Huan
2014-09-05 13:52:39 +08:00
committed by York Sun
parent 52d00a812a
commit c82e9de400
2 changed files with 18 additions and 1 deletions
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5
doc/README.fsl-esdhc Normal file
View File

@@ -0,0 +1,5 @@
CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
Accessing ESDHC registers can be determined by ESDHC IP's endian
mode or processor's endian mode.

14
include/fsl_esdhc.h
View File

@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
}; };
/* Select the correct accessors depending on endianess */ /* Select the correct accessors depending on endianess */
#if __BYTE_ORDER == __LITTLE_ENDIAN #if defined CONFIG_SYS_FSL_ESDHC_LE
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
#define esdhc_clrbits32 clrbits_le32
#define esdhc_setbits32 setbits_le32
#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
#define esdhc_read32 in_be32
#define esdhc_write32 out_be32
#define esdhc_clrsetbits32 clrsetbits_be32
#define esdhc_clrbits32 clrbits_be32
#define esdhc_setbits32 setbits_be32
#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32 in_le32 #define esdhc_read32 in_le32
#define esdhc_write32 out_le32 #define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32 #define esdhc_clrsetbits32 clrsetbits_le32