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powerpc/mpc8xxx: Add memory reset control

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JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2013-06-25 11:37:48 -07:00
parent b61e061566
commit c63e137014
16 changed files with 131 additions and 21 deletions
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2
board/freescale/p1_twr/ddr.c
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@@ -59,7 +59,7 @@ phys_size_t fixed_sdram(void)
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {