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stm32mp1: ram: change ddr speed to kHz

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Allow fractional support in DDR tools.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay
2019-04-10 14:09:23 +02:00
committed by Patrice Chotard
parent 0cb1aa9409
commit c60fed14f6
6 changed files with 15 additions and 15 deletions
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2
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
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@@ -17,7 +17,7 @@
* Tc > + 85C : N * Tc > + 85C : N
*/ */
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43" #define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43"
#define DDR_MEM_SPEED 533 #define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000 #define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401 #define DDR_MSTR 0x00041401

2
arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
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@@ -18,7 +18,7 @@
*/ */
#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" #define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
#define DDR_MEM_SPEED 533 #define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000 #define DDR_MEM_SIZE 0x40000000
#define DDR_MSTR 0x00040401 #define DDR_MSTR 0x00040401

4
doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt
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@@ -16,7 +16,7 @@ included in STM32 Cube tool
info attributes: info attributes:
---------------- ----------------
- st,mem-name : name for DDR configuration, simple string for information - st,mem-name : name for DDR configuration, simple string for information
- st,mem-speed : DDR expected speed for the setting in MHz - st,mem-speed : DDR expected speed for the setting in kHz
- st,mem-size : DDR mem size in byte - st,mem-size : DDR mem size in byte
@@ -173,7 +173,7 @@ Example:
"ddrphycapb"; "ddrphycapb";
st,mem-name = "DDR3 2x4Gb 533MHz"; st,mem-name = "DDR3 2x4Gb 533MHz";
st,mem-speed = <533>; st,mem-speed = <533000>;
st,mem-size = <0x40000000>; st,mem-size = <0x40000000>;
st,ctl-reg = < st,ctl-reg = <

4
drivers/ram/stm32mp1/stm32mp1_ddr.c
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@@ -373,7 +373,7 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
panic("ddr power init failed\n"); panic("ddr power init failed\n");
debug("name = %s\n", config->info.name); debug("name = %s\n", config->info.name);
debug("speed = %d MHz\n", config->info.speed); debug("speed = %d kHz\n", config->info.speed);
debug("size = 0x%x\n", config->info.size); debug("size = 0x%x\n", config->info.size);
/* /*
* 1. Program the DWC_ddr_umctl2 registers * 1. Program the DWC_ddr_umctl2 registers
@@ -389,7 +389,7 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
/* 1.2. start CLOCK */ /* 1.2. start CLOCK */
if (stm32mp1_ddr_clk_enable(priv, config->info.speed)) if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
panic("invalid DRAM clock : %d MHz\n", panic("invalid DRAM clock : %d kHz\n",
config->info.speed); config->info.speed);
/* 1.3. deassert reset */ /* 1.3. deassert reset */

4
drivers/ram/stm32mp1/stm32mp1_ddr.h
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@@ -157,7 +157,7 @@ struct stm32mp1_ddrphy_cal {
struct stm32mp1_ddr_info { struct stm32mp1_ddr_info {
const char *name; const char *name;
u16 speed; /* in MHZ */ u32 speed; /* in kHZ */
u32 size; /* memory size in byte = col * row * width */ u32 size; /* memory size in byte = col * row * width */
}; };
@@ -172,7 +172,7 @@ struct stm32mp1_ddr_config {
struct stm32mp1_ddrphy_cal p_cal; struct stm32mp1_ddrphy_cal p_cal;
}; };
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed); int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,

14
drivers/ram/stm32mp1/stm32mp1_ram.c
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@@ -20,7 +20,7 @@ static const char *const clkname[] = {
"ddrphyc" /* LAST clock => used for get_rate() */ "ddrphyc" /* LAST clock => used for get_rate() */
}; };
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
{ {
unsigned long ddrphy_clk; unsigned long ddrphy_clk;
unsigned long ddr_clk; unsigned long ddr_clk;
@@ -43,13 +43,13 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
priv->clk = clk; priv->clk = clk;
ddrphy_clk = clk_get_rate(&priv->clk); ddrphy_clk = clk_get_rate(&priv->clk);
debug("DDR: mem_speed (%d MHz), RCC %d MHz\n", debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); mem_speed, (u32)(ddrphy_clk / 1000));
/* max 10% frequency delta */ /* max 10% frequency delta */
ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
if (ddr_clk > (mem_speed * 1000 * 100)) { if (ddr_clk > (mem_speed * 100)) {
pr_err("DDR expected freq %d MHz, current is %d MHz\n", pr_err("DDR expected freq %d kHz, current is %d kHz\n",
mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); mem_speed, (u32)(ddrphy_clk / 1000));
return -EINVAL; return -EINVAL;
} }