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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD
2013-12-06 14:26:51 +01:00
parent 7988bd4ed6 18a02e8050
commit c35cf8dc9f
53 changed files with 1745 additions and 261 deletions
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37
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@@ -18,7 +18,6 @@
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
#define PHY_EN_DYN_PWRDN (0x1 << 20)
@@ -29,7 +28,6 @@
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
#define MT47H128M16RT25E_RATIO 0x80
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
@@ -38,7 +36,6 @@
#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
@@ -49,7 +46,6 @@
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
#define MT41J128MJT125_RATIO 0x40
#define MT41J128MJT125_INVERT_CLKOUT 0x1
#define MT41J128MJT125_RD_DQS 0x3B
@@ -58,6 +54,12 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
/* Micron MT41J256M16JT-125 */
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
/* Micron MT41J256M8HX-15E */
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
@@ -66,7 +68,6 @@
#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
#define MT41J256M8HX15E_RATIO 0x40
#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
#define MT41J256M8HX15E_RD_DQS 0x3B
@@ -83,7 +84,6 @@
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
#define MT41K256M16HA125E_RD_DQS 0x38
@@ -100,7 +100,6 @@
#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
#define MT41J512M8RH125_RATIO 0x80
#define MT41J512M8RH125_INVERT_CLKOUT 0x0
#define MT41J512M8RH125_RD_DQS 0x3B
@@ -117,7 +116,6 @@
#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
#define K4B2G1646EBIH9_RATIO 0x80
#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
#define K4B2G1646EBIH9_RD_DQS 0x35
@@ -149,18 +147,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr);
struct ddr_cmd_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv1[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int resv1[3];
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv2[8];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv3[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int resv3[3];
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv4[8];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv5[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int resv5[3];
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv6[3];
};
@@ -197,24 +192,21 @@ struct ddr_regs {
unsigned int cm0configclk; /* offset 0x010 */
unsigned int resv1[2];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv2[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int resv2[3];
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv3[4];
unsigned int cm1config; /* offset 0x040 */
unsigned int cm1configclk; /* offset 0x044 */
unsigned int resv4[2];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv5[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int resv5[3];
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv6[4];
unsigned int cm2config; /* offset 0x074 */
unsigned int cm2configclk; /* offset 0x078 */
unsigned int resv7[2];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv8[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int resv8[3];
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv9[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
@@ -243,17 +235,14 @@ struct cmd_control {
unsigned long cmd0csratio;
unsigned long cmd0csforce;
unsigned long cmd0csdelay;
unsigned long cmd0dldiff;
unsigned long cmd0iclkout;
unsigned long cmd1csratio;
unsigned long cmd1csforce;
unsigned long cmd1csdelay;
unsigned long cmd1dldiff;
unsigned long cmd1iclkout;
unsigned long cmd2csratio;
unsigned long cmd2csforce;
unsigned long cmd2csdelay;
unsigned long cmd2dldiff;
unsigned long cmd2iclkout;
};
@@ -267,8 +256,6 @@ struct ddr_data {
unsigned long datagiratio0;
unsigned long datafwsratio0;
unsigned long datawrsratio0;
unsigned long datauserank0delay;
unsigned long datadldiff0;
};
/**

3
arch/arm/include/asm/arch-davinci/hardware.h
View File

@@ -478,8 +478,9 @@ struct davinci_syscfg_regs {
dv_reg rsvd[13];
dv_reg kick0;
dv_reg kick1;
dv_reg rsvd1[53];
dv_reg rsvd1[52];
dv_reg mstpri[3];
dv_reg rsvd2;
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;

2
arch/arm/include/asm/arch-omap3/clock.h
View File

@@ -27,8 +27,6 @@
#define ICK_DSS_ON 0x00000001
#define FCK_CAM_ON 0x00000001
#define ICK_CAM_ON 0x00000001
#define FCK_PER_ON 0x0003ffff
#define ICK_PER_ON 0x0003ffff
/* Used to index into DPLL parameter tables */
typedef struct {

1
arch/arm/include/asm/arch-omap3/omap3.h
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@@ -55,6 +55,7 @@ struct control_prog_io {
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
/* General Purpose Timers */
#define OMAP34XX_GPT1 0x48318000

4
arch/arm/include/asm/arch-omap4/sys_proto.h
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@@ -16,6 +16,10 @@
DECLARE_GLOBAL_DATA_PTR;
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
struct omap_sysinfo {
char *board_string;
};

3
arch/arm/include/asm/arch-omap5/clock.h
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@@ -137,6 +137,9 @@
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)

4
arch/arm/include/asm/arch-omap5/omap.h
View File

@@ -64,6 +64,9 @@
/* QSPI */
#define QSPI_BASE 0x4B300000
/* SATA */
#define DWC_AHSATA_BASE 0x4A140000
/*
* Hardware Register Details
*/
@@ -239,6 +242,7 @@ struct ctrl_ioregs {
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
u32 ctrl_emif_sdram_config_ext_final;
u32 ctrl_ddr_ctrl_ext_0;
};

48
arch/arm/include/asm/arch-omap5/sata.h Normal file
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@@ -0,0 +1,48 @@
/*
* SATA Wrapper Register map
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TI_SATA_H
#define _TI_SATA_H
/* SATA Wrapper module */
#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100)
/* SATA PHY Module */
#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800)
/* SATA Wrapper register offsets */
#define TI_SATA_SYSCONFIG 0x00
#define TI_SATA_CDRLOCK 0x04
/* Register Set */
#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16)
#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4)
#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2)
/* Standby modes */
#define TI_SATA_STANDBY_FORCE 0x0
#define TI_SATA_STANDBY_NO (0x1 << 4)
#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4)
#define TI_SATA_STANDBY_SMART (0x2 << 4)
/* Idle modes */
#define TI_SATA_IDLE_FORCE 0x0
#define TI_SATA_IDLE_NO (0x1 << 2)
#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2)
#define TI_SATA_IDLE_SMART (0x2 << 2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int omap_sata_init(void);
#else
static inline int omap_sata_init(void)
{
return 0;
}
#endif /* CONFIG_SCSI_AHCI_PLAT */
#endif /* _TI_SATA_H */

14
arch/arm/include/asm/emif.h
View File

@@ -581,7 +581,6 @@
(0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */
struct emif_reg_struct {
@@ -641,7 +640,9 @@ struct emif_reg_struct {
u32 emif_ddr_phy_ctrl_2;
u32 padding7[12];
u32 emif_rd_wr_exec_thresh;
u32 padding8[55];
u32 padding8[7];
u32 emif_ddr_phy_status[21];
u32 padding9[27];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@@ -690,6 +691,9 @@ struct emif_reg_struct {
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
u32 padding[22];
u32 emif_ddr_fifo_misaligned_clear_1;
u32 emif_ddr_fifo_misaligned_clear_2;
};
struct dmm_lisa_map_regs {
@@ -1139,6 +1143,11 @@ struct lpddr2_mr_regs {
s8 mr16;
};
struct read_write_regs {
u32 read_reg;
u32 write_reg;
};
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
@@ -1167,4 +1176,5 @@ extern u32 *const T_den;
void config_data_eye_leveling_samples(u32 emif_base);
u32 emif_sdram_type(void);
const struct read_write_regs *get_bug_regs(u32 *iterations);
#endif

10
arch/arm/include/asm/omap_common.h
View File

@@ -226,6 +226,7 @@ struct prcm_regs {
u32 cm_l3init_hsusbotg_clkctrl;
u32 cm_l3init_hsusbtll_clkctrl;
u32 cm_l3init_p1500_clkctrl;
u32 cm_l3init_sata_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
@@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs {
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
u32 control_usbotghs_ctrl;
u32 control_phy_power_sata;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
@@ -605,6 +607,14 @@ static inline u8 is_omap54xx(void)
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
}
#define DRA7XX 0x07000000
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == DRA7XX);
}
#endif
/*