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https://xff.cz/git/u-boot/
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armv8: ls1088aqds: Add IFC-NOR as boot source for LS1088
IFC-NOR and QSPI-NOR pins are multiplexed on SoC, so they cannot be accessed simultaneously. IFC-NOR can be accessed along with SD-BOOT. Ls1088aqds_sdcard_ifc_defconfig is default config for SD boot and IFC-NOR to be used as flash. This allows writing to IFC-NOR flash. QSPI and DSPI cannot be accessed in this defconfig. IFC-NOR image is generated using ls1088aqds_defconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
@@ -19,6 +19,43 @@
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0 0 0x5 0x80000000 0x08000000
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2 0 0x5 0x30000000 0x00010000
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3 0 0x5 0x20000000 0x00010000>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@2,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1 0x0 0x10000>;
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};
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fpga: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus", "fsl,ls1088aqds-fpga",
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"fsl,fpga-qixis";
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reg = <0x2 0x0 0x0000100>;
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bank-width = <1>;
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device-width = <1>;
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ranges = <0 2 0 0x100>;
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};
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};
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&dspi {
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&dspi {
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bus-num = <0>;
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bus-num = <0>;
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status = "okay";
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status = "okay";
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@@ -75,6 +75,11 @@
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reg-names = "QuadSPI", "QuadSPI-memory";
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reg-names = "QuadSPI", "QuadSPI-memory";
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num-cs = <4>;
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num-cs = <4>;
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};
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x2240000 0x0 0x20000>;
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interrupts = <0 21 0x4>; /* Level high type */
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};
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usb0: usb3@3100000 {
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usb0: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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compatible = "fsl,layerscape-dwc3";
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@@ -15,6 +15,8 @@ F: board/freescale/ls1088a/
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F: include/configs/ls1088aqds.h
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F: include/configs/ls1088aqds.h
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F: configs/ls1088aqds_qspi_defconfig
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F: configs/ls1088aqds_qspi_defconfig
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F: configs/ls1088aqds_sdcard_qspi_defconfig
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F: configs/ls1088aqds_sdcard_qspi_defconfig
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F: configs/ls1088aqds_defconfig
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F: configs/ls1088aqds_sdcard_ifc_defconfig
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LS1088AQDS_QSPI_SECURE_BOOT BOARD
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LS1088AQDS_QSPI_SECURE_BOOT BOARD
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M: Udit Agarwal <udit.agarwal@nxp.com>
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M: Udit Agarwal <udit.agarwal@nxp.com>
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43
configs/ls1088aqds_defconfig
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43
configs/ls1088aqds_defconfig
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@@ -0,0 +1,43 @@
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CONFIG_ARM=y
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CONFIG_TARGET_LS1088AQDS=y
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CONFIG_SYS_TEXT_BASE=0x30100000
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_I2C=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_OF_CONTROL=y
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CONFIG_FSL_IFC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SCSI_AHCI=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_NETDEVICES=y
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CONFIG_E1000=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE=y
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CONFIG_SYS_NS16550=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_FSL_LS_PPA=y
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CONFIG_USB=y
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CONFIG_USB_GADGET=y
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CONFIG_CMD_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_STORAGE=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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# CONFIG_USE_BOOTCOMMAND is not set
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54
configs/ls1088aqds_sdcard_ifc_defconfig
Normal file
54
configs/ls1088aqds_sdcard_ifc_defconfig
Normal file
@@ -0,0 +1,54 @@
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CONFIG_ARM=y
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CONFIG_TARGET_LS1088AQDS=y
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CONFIG_SYS_TEXT_BASE=0x80400000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_FSL_LS_PPA=y
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CONFIG_SPL_MMC_SUPPORT=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_PARTITIONS=y
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CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
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CONFIG_SD_BOOT=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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# CONFIG_USE_BOOTCOMMAND is not set
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CONFIG_SPL=y
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CONFIG_SPL_BUILD=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_I2C_SUPPORT=y
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FSL_IFC=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SCSI_AHCI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_NETDEVICES=y
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CONFIG_E1000=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE=y
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CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_GADGET=y
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@@ -27,7 +27,6 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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@@ -41,6 +40,8 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#else
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#else
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#define CONFIG_QIXIS_I2C_ACCESS
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#define CONFIG_SYS_I2C_EARLY_INIT
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#endif
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#endif
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@@ -89,13 +90,14 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TAVDS(0x6) | \
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FTIM0_NOR_TEAHC(0x5))
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) |\
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FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TCH(0x8) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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