From c1403bd080bc517c9dc6f507ee12b62fa85153bc Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 25 Apr 2024 16:46:13 +0200 Subject: [PATCH] spl: Try loading bitstream first, before falling back to fpga_load There's no other way to load bitstream file to Zynq 7000 via SPL otherwise, and SPL just reports: zynq_validate_bitstream: Bitstream is not validated yet (diff 6c) spl_fit_upload_fpga: Cannot load the image to the FPGA This is similar to code in boot/image-board.c Signed-off-by: Ondrej Jirman --- common/spl/spl_fit.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c4c123413cb..fd3ab10c3f2 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -615,8 +615,11 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node, compatible); } - ret = fpga_load(devnum, (void *)fpga_image->load_addr, - fpga_image->size, BIT_FULL, flags); + ret = fpga_loadbitstream(devnum, (void *)fpga_image->load_addr, + fpga_image->size, BIT_FULL); + if (ret) + ret = fpga_load(devnum, (void *)fpga_image->load_addr, + fpga_image->size, BIT_FULL, flags); if (ret) { printf("%s: Cannot load the image to the FPGA\n", __func__); return ret;