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armv8: fsl-lsch3: Make CCN-504 related code conditional

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LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Ashish Kumar
2017-08-18 10:54:36 +05:30
committed by York Sun
parent c8bc3c0c9f
commit c055cee195
3 changed files with 13 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
README
View File

@@ -322,6 +322,10 @@ build a config tool - later.
Defined For SoC that has cache coherent interconnect Defined For SoC that has cache coherent interconnect
CCN-400 CCN-400
CONFIG_SYS_FSL_HAS_CCN504
Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured: The following options need to be configured:
- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. - CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.

4
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
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@@ -61,6 +61,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR select SYS_FSL_DDR
select SYS_FSL_DDR_LE select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_CCN504
select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_DDR4
@@ -269,6 +270,9 @@ config SYS_FSL_IFC_BANK_COUNT
config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCI400
bool bool
config SYS_FSL_HAS_CCN504
bool
config SYS_FSL_HAS_DP_DDR config SYS_FSL_HAS_DP_DDR
bool bool

8
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1: 1:
#ifdef CONFIG_FSL_LSCH3 #if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */ /* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_ARCH_LS2080A #ifdef CONFIG_ARCH_LS2080A
@@ -171,7 +171,7 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C ldr x1, =0x00FF000C
bl ccn504_set_qos bl ccn504_set_qos
#endif #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE #ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */ /* Set the SMMU page size in the sACR register */
@@ -338,7 +338,9 @@ get_svr:
ldr x1, =FSL_LSCH3_SVR ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1] ldr w0, [x1]
ret ret
#endif
#ifdef CONFIG_SYS_FSL_HAS_CCN504
hnf_pstate_poll: hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout /* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7 * clobber x1, x2, x3, x4, x6, x7
@@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
mov lr, x29 mov lr, x29
ret ret
ENDPROC(__asm_flush_l3_dcache) ENDPROC(__asm_flush_l3_dcache)
#endif #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP #ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */ /* Keep literals not used by the secondary boot code outside it */