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Fix the incorrect DDR clk freq reporting on 8536DS

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On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
This commit is contained in:
Jason Jin
2008-09-27 14:40:57 +08:00
committed by Andrew Fleming-AFLEMING
parent bac6a1d1fa
commit c0391111c3
4 changed files with 12 additions and 3 deletions
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3
cpu/mpc85xx/cpu.c
View File

@@ -85,7 +85,8 @@ int checkcpu (void)
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif

3
cpu/mpc85xx/speed.c
View File

@@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_DDR_CLK_FREQ
{
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}